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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 263 occurrences of 139 keywords
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Results
Found 635 publication records. Showing 635 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
128 | Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme |
Application of Reconfigurable CORDIC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(2-3), pp. 211-221, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
103 | Jie Zhou 0007, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong |
Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: 10th IEEE International Conference on High Performance Computing and Communications, HPCC 2008, 25-27 Sept. 2008, Dalian, China, pp. 182-189, 2008, IEEE Computer Society, 978-0-7695-3352-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
103 | Nariankadu D. Hemkumar, Joseph R. Cavallaro |
Efficient complex matrix transformations with CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 122-129, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
101 | Julio Villalba, J. C. Arrabal, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera |
Radix-4 Vectoring Cordic Algorithm And Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 55-64, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
radix-4 vectoring CORDIC algorithm, radix-4 vectoring CORDIC architectures, vectoring mode, microrotations, zero skipping technique, recursive architectures, matrix triangularization, rotation angle, computational complexity, complexity, parallel architectures, singular value decomposition, SVD, signal processing, digital arithmetic, digital arithmetic, matrix algebra, pipelined architectures |
91 | Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya |
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 15(11), pp. 1463-1474, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
91 | Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme |
Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(2), pp. 155-166, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
91 | Shen-Fu Hsiao, Jen-Yin Chen |
Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 20(3), pp. 267-278, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
88 | Bimal Gisutham, Thambipillai Srikanthan, Vijayan K. Asari |
A High Speed Flat CORDIC Based Neuron with Multi-Level Activation Function for Robust Pattern Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 87-94, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CORDIC based neuron, robust pattern recognition, multiple valued logic neuron, neural network implementation, real-time pattern recognition, Flat CORDIC, neural networks, image processing, complexity, activation function |
86 | Nariankadu D. Hemkumar, Joseph R. Cavallaro |
Redundant and On-Line CORDIC for Unitary Transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(8), pp. 941-954, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
unitary transformations, two-sided unitary transformation, Jacobi-like methods, complex matrices, special-purpose processor array architectures, nonredundant CORDIC, online CORDIC, redundant CORDIC, Coordinate Rotation Digital Computer, parallel algorithms, parallel algorithms, computational complexity, parallel architectures, singular value decompositions, digital arithmetic, matrix algebra, eigenvalue, CORDIC, special purpose computers, eigenvalues and eigenfunctions, matrices |
83 | Tomás Lang, Elisardo Antelo |
CORDIC Vectoring with Arbitrary Target Value. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 108-115, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Computer arithmetic, VLSI architectures, rotations, CORDIC, elementary functions |
78 | Jie Zhou 0007, Yong Dou, Yuanwu Lei, Yazhuo Dong |
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings, pp. 254-259, 2008, Springer, 978-3-540-78609-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
78 | Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu |
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 422-427, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
78 | Chang Yong Kang, Earl E. Swartzlander Jr. |
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 111-119, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
78 | Andrew P. Paplinski, Nandita Bhattacharjee, Charles Greif |
Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 254-261, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
78 | Jack E. Volder |
The Birth of Cordic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(2), pp. 101-105, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
78 | Marco Bekooij, Jos Huisken, Katarzyna Nowak |
Numerical Accuracy of Fast Fourier Transforms with CORDIC Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(2), pp. 187-193, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
78 | Jae-Hyuck Kwak, Jae Hun Choi, Earl E. Swartzlander Jr. |
High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(2), pp. 167-177, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
78 | Tomás Lang, Elisardo Antelo |
CORDIC-Based Computation of ArcCos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(1), pp. 19-38, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
78 | Tomás Lang, Elisardo Antelo |
CORDIC-based computation of arccos and arcsin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 132-143, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
76 | Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin |
A High-Efficiency Vector Interpolator Using Redundant CORDIC Arithmetic in Power-Aware 3-D Graphics Rendering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2006), 4-7 December 2006, Taipei, Taiwan, pp. 44-49, 2006, IEEE Computer Society, 0-7695-2736-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Redundant CORDIC arithmetic, 3-D vector interpolation, high-throughput, CORDIC algorithm |
71 | Fabian Angarita, Ma José Canet, T. Sansaloni, A. Perez-Pascual, Javier Valls |
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(2), pp. 181-191, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
wireless LAN, OFDM, cordic |
71 | Tomás Lang, Elisardo Antelo |
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(3), pp. 347-361, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
vector normalization, geometry transforms, graphics processor, CORDIC, 3D rotations |
71 | Konstantinos Sarrigeorgidis, Jan M. Rabaey |
Ultra Low Power CORDIC Processor for Wireless Communication Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 38(2), pp. 115-130, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cordic arithmetic, wireless communications, low power design, least squares, QR decomposition, redundant arithmetic |
71 | Javier Valls, Martin Kuhlmann, Keshab K. Parhi |
Evaluation of CORDIC Algorithms for FPGA Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 32(3), pp. 207-222, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, CORDIC, redundant arithmetic, Two's complement |
71 | Elisardo Antelo, Tomás Lang, Javier D. Bruguera |
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 727-739, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Very-high radix algorithms, selection by rounding, angle and modulus calculation, rotation, CORDIC |
71 | Ray Andraka |
A Survey of CORDIC Algorithms for FPGA Based Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 191-200, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
polar conversion, vector magnitude, CORDIC, sine, cosine |
71 | Julio Villalba, José Antonio Hidalgo López, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera |
CORDIC Architectures with Parallel Compensation of the Scale Factor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 258-269, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Parallel Architecture, CORDIC algorithm, Scale Factor, Redundant Arithmetic |
66 | Xinbiao Gan, Kui Dai, Libo Huang, Li Shen 0007, Zhiying Wang 0003 |
A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MUE ![In: 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 24-26 April 2008, Busan, Korea, pp. 83-86, 2008, IEEE Computer Society, 978-0-7695-3134-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
66 | Tso-Bing Juang |
Area/Delay Efficient Recoding Methods for Parallel CORDIC Rotations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1539-1542, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
66 | Zhaohui Liu, Kevin Dickson, John V. McCanny |
A floating-point CORDIC based SVD processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 194-203, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
66 | Abhishek Singh 0001, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel |
Comparison of Branching CORDIC Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 215-225, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
66 | Javier D. Bruguera, Nicolás Guil, Tomás Lang, Julio Villalba, Emilio L. Zapata |
Cordic based parallel/pipelined architecture for the Hough transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 12(3), pp. 207-221, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
66 | Feng Zhou, Peter Kornerup |
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 180-187, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
59 | Javier Hormigo, Julio Villalba, Emilio L. Zapata |
CORDIC Processor for Variable-Precision Interval Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 37(1), pp. 21-39, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interval arithmetic, CORDIC, reliable computing, variable precision |
59 | Jen-Chuan Chih, Sau-Gee Chen |
Fast CORDIC Algorithm Based on a New Recoding Scheme for Rotation Angles and Variable Scale Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 19-29, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
variable scale factor, table lookup method, residual angle and scale factor recoding, CORDIC algorithm |
59 | Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr. |
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 68-72, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Low latency CORDIC architecture, Folded-transistor design, Area optimization |
59 | Julio Villalba, Tomás Lang |
Low latency word serial CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 124-131, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
word serial CORDIC, vectoring operation modes, digital arithmetic, iterations, scaling factor |
59 | Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata |
Digit On-line Large Radix CORDIC Rotator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 246-257, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm |
54 | Oskar Mencer, Wayne Luk |
Parameterized High Throughput Function Evaluation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 36(1), pp. 17-25, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGAs, function approximation, CORDIC, lookup table, rational approximation |
54 | M. G. Buddika Sumanasena |
A Scale Factor Correction Scheme for the CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(8), pp. 1148-1152, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Elisardo Antelo, Julio Villalba, Emilio L. Zapata |
A Low-Latency Pipelined 2D and 3D CORDIC Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(3), pp. 404-417, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Arithmetic and Logic Structures, Algorithms, Computer arithmetic, High-Speed Arithmetic |
54 | Koushik Maharatna, Karim El-Shabrawy, Bashir M. Al-Hashimi |
Reduced Z-datapath Cordic Rotator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3374-3377, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
54 | Chi-Li Yu, Tzu-Hao Yu, An-Yeu Wu |
On the Fixed-Point Properties of Mixed-Scaling-Rotation Cordic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 430-435, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | R. Stapenhurst, Koushik Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan |
On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3002-3005, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Mihai Sima, John Glossner, Daniel Iancu, Hua Ye 0003, Andrei Iancu, A. Joseph Hoane |
CORDIC-Augmented Sandbridge Processor for Channel Equalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 152-161, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Jen-Chuan Chih, Kun-Lung Chen, Sau-Gee Chen |
A CORDIC processor with efficient table-lookup schemes for rotations and on-line scale factor compensations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3315-3318, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
54 | Satish Ravichandran, Vijayan K. Asari |
Pre-computatio of Rotatio Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 215-216, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
54 | Shen-Fu Hsiao |
A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 455-458, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
54 | Roberto Sarmiento, V. de Armas, José Francisco López, Juan A. Montiel-Nelson, Antonio Núñez |
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 18-30, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
54 | Julio Villalba, Emilio L. Zapata, Elisardo Antelo, Javier D. Bruguera |
Radix-4 Vectoring CORDIC Algorithm and Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(2), pp. 127-147, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
54 | Gerben J. Hekstra, Ed F. Deprettere |
Floating point Cordic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings., pp. 130-137, 1993, IEEE Computer Society/, 0-8186-3862-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
52 | Tomás Lang, Elisardo Antelo |
CORDIC Vectoring with Arbitrary Target Value. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(7), pp. 736-749, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Extended CORDIC functions, inverse kinematics computations, computer arithmetic, rotations, CORDIC |
52 | Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr. |
Hybrid CORDIC Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 46(11), pp. 1202-1207, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Givens transformation, planary rotator, CORDIC architecture, elementary function, CORDIC algorithm |
52 | Kishore Kota, Joseph R. Cavallaro |
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 769-779, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
numerical accuracy, hardware tradeoffs, CORDIC arithmetic, special-purpose processors, coordinate rotation digital computer, real-time signal processing, Y-reduction mode, inverse tangent function, floating-point CORDIC, special-purpose arrays, signal processing, digital arithmetic, hybrid architecture, implementation complexity |
52 | Jean Duprat, Jean-Michel Muller |
The CORDIC Algorithm: New Results for Fast VLSI Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(2), pp. 168-178, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
sign functions, fast VLSI implementation, signed-digit implementation, carry-save representation, branching CORDIC method, constant normalization factor, online delay, cosine functions, VLSI, signal processing, digital arithmetic, CORDIC algorithm |
52 | Milos D. Ercegovac, Tomás Lang |
Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(6), pp. 725-740, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
online CORDIC, redundant CORDIC, matrix triangularization, angles, digit-serial addition, online multiplication, Givens' rotations, singular value decomposition, SVD, digital arithmetic, rotations, division, square root, scaling factors, floating-point representations |
49 | Mihai Sima, Michael McGuire |
Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 13-18, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Ignacio Bravo Muñoz, Pedro Jiménez, Manuel Mazo 0001, José Luis Lázaro, Alfredo Gardel Vicente |
Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin |
High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2006), 4-7 December 2006, Taipei, Taiwan, pp. 191-196, 2006, IEEE Computer Society, 0-7695-2736-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-power, DCT, CORDIC, IDCT |
46 | Eckhard Grass, Bodhisatya Sarker, Koushik Maharatna |
A Dual-Mode Synchronous/Asynchronous CORDIC Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 76-83, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
CORDIC processor, dual-mode, synchronous, asynchronous, self-timed |
46 | Jason M. Musicer, Jan M. Rabaey |
MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 102-107, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
CORDIC, digital logic, current mode logic, low-energy design |
46 | Elisardo Antelo, Javier D. Bruguera, Tomás Lang, Julio Villalba, Emilio L. Zapata |
High Radix Cordic Rotation Based on Selection by Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par, Vol. II ![In: Euro-Par '96 Parallel Processing, Second International Euro-Par Conference, Lyon, France, August 26-29, 1996, Proceedings, Volume II, pp. 155-164, 1996, Springer, 3-540-61627-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Rotation mode, High radix algorithm, CORDIC algorithm |
46 | Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata |
Redundant CORDIC Rotator Based on Parallel Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 172-179, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
High speed processor, Parallel prediction, Parallel architecture, CORDIC algorithm, Redundant arithmetic |
42 | Roberto Gutierrez, Javier Valls |
Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(1), pp. 25-33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
atan(Y/X), FPGA, Wireless communication, CORDIC |
42 | Robin Pottathuparambil, Ron Sass |
A parallel/vectorized double-precision exponential core to accelerate computational science applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 285, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
exponential core, fpga, cordic |
42 | Jarmo Takala, Konsta Punkka |
Scalable FFT Processors and Pipelined Butterfly Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(2-3), pp. 113-123, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
parallel processing, application-specific integrated circuit, CORDIC, distributed arithmetic, radix-2 |
42 | Ian D. Walker, Joseph R. Cavallaro |
Parallel VLSI architectures for real-time kinematics of redundant robots. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 9(1-2), pp. 25-43, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
cordic arithmetic, kinematic redundancy, VLSI, Robot kinematics, pseudoinverse |
41 | Malay K. Ganai, Franjo Ivancic |
Efficient decision procedure for non-linear arithmetic constraints using CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, FMCAD 2009, 15-18 November 2009, Austin, Texas, USA, pp. 61-68, 2009, IEEE, 978-1-4244-4966-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | José Luis Sánchez, Higinio Mora Mora, Jerónimo Mora Pascual, Antonio Jimeno |
Architecture implementation of an improved decimal CORDIC method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 95-100, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Erkka Laulainen, Lauri Koskinen, Marko Kosunen, Kari Halonen |
Compass tilt compensation algorithm using CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1188-1191, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Katsutoshi Seki, Tomoyoshi Kobori, James Okello, Masao Ikekawa |
A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China, pp. 639-644, 2007, IEEE, 1-4244-1222-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Elisardo Antelo, Julio Villalba |
Low Latency Pipelined Circular CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 280-287, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Suchitra Sathyanarayana, S. Sukthankar, Thambipillai Srikanthan, Christopher T. Clarke |
Elimination of sign precomputation in flat CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3319-3322, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe |
FPGA-Efficient Hybrid LUT/CORDIC Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 933-937, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Shin'ichi Shiraishi, Miki Haseyama, Hideo Kitajima |
A cost-effective and high-precision architecture for CORDIC-based adaptive lattice filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 297-300, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri |
Fault-Tolerant High-Performance Cordic Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings, pp. 164-172, 2000, IEEE Computer Society, 0-7695-0719-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
41 | David Lewis |
Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 194-203, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Javier Hormigo, Julio Villalba, Emilio L. Zapata |
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 186-193, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Elisardo Antelo, Tomás Lang, Javier D. Bruguera |
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 204-, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | Julio Villalba, Tomás Lang, Emilio L. Zapata |
Parallel Compensation of Scale Factor for the CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(3), pp. 227-241, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Christian V. Schimpfle, Sven Simon 0001, Josef A. Nossek |
Low Power CORDIC Implementation Using Redundant Number Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 154-161, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
41 | D. E. Metafas, Constantinos E. Goutis |
A floating-point advanced cordic processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 10(1), pp. 53-65, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
37 | Hongzhi Wang 0003, Pierre Leray, Jacques Palicot |
An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 746-750, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Jie Chen 0002, K. J. Ray Liu |
Efficient architecture and design of an embedded video coding engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 3(3), pp. 285-297, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles |
Parameterized Function Evaluation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 544-554, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Sau-Gee Chen, Chin-Chi Chang |
A new efficient algorithm for singular value decomposition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 523-526, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Jürgen Götze, Steffen Paul, Matthias Sauer 0001 |
An Efficient Jacobi-like Algorithm for Parallel Eigenvalue Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(9), pp. 1058-1065, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Jacobi-like algorithm, parallel eigenvalue computation, symmetric eigenvalue problems, CORDIC processor, CORDIC angle sequence, Jacobi rotation, linear convergence, approximate rotations, scaling computation, parallel algorithms, signal processing, digital signal processing, matrix algebra, convergence of numerical methods, eigenvalues and eigenfunctions, matrix computation, fast implementations, quadratic convergence, eigenvalue computation |
34 | Terence K. Rodrigues, Earl E. Swartzlander Jr. |
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 59(4), pp. 522-531, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
angle rotation, sine computation, cosine computation, CORDIC algorithm |
34 | Bipul Das, Swapna Banerjee |
A CORDIC based array architecture for complex discrete wavelet transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001, pp. 79-84, 2001, ACM, 1-58113-351-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
complex discrete wavelet transform, image padding, FPGA, FIR filter, CORDIC |
34 | Dhananjay S. Phatak |
Comments on Duprat and Muller's Branching CORDIC Paper. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 47(9), pp. 1037-1040, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Branching CORDIC, constant scale factor, errata, corrections, signed-digit representation |
34 | Shen-Fu Hsiao, Jean-Marc Delosme |
Householder CORDIC Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(8), pp. 990-1001, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Householder reflections, parallel algorithms, VLSI, computer arithmetic, CORDIC |
34 | Steffen Paul, Jürgen Götze, Matthias Sauer 0001 |
Error Analysis of CORDIC-Based Jacobi Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(7), pp. 947-951, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
eigenvalue calculation, Jacobi algorithms, approximate rotations, Error analysis, CORDIC |
34 | Helmut Hahn, Dirk Timmermann, Bedrich J. Hosticka, Bernold Rix |
A Unified and Division-Free CORDIC Argument Reduction Method with Unlimited Convergence Domain Including Inverse Hyperbolic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(11), pp. 1339-1344, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
CORDIC argument reduction method, convergence domain, inverse hyperbolic functions, unified division-free argument reduction method, floating point implementation, fixed point implementation, digital arithmetic, mathematics computing |
34 | Yu Hen Hu, S. Naganathan |
An Angle Recoding Method for CORDIC Algorithm Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(1), pp. 99-102, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
angle recording method, CORDIC algorithm implementation, coordinate rotation digital computer, iterative arithmetic algorithm, generalized vector rotations, elementary rotation angles, signal processing, digital arithmetic, greedy algorithm |
34 | Dirk Timmermann, Helmut Hahn, Bedrich J. Hosticka |
Low Latency Time CORDIC Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 1010-1015, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
constant scale factor, redundant addition, latency time, computational complexity, parallel architecture, iterative methods, digital arithmetic, adders, number theory, CORDIC algorithms |
34 | Jeong-A Lee, Tomás Lang |
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(8), pp. 1016-1025, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
rotation direction, angle calculation, constant-factor redundant-CORDIC, plane rotations, correcting iterations, radix-4, convergence, iterative methods, digital arithmetic, number theory, convergence of numerical methods, algorithm theory, scale factor, radix-2 |
34 | Xiaobo Hu 0001, Ronald G. Harber, Steven C. Bass |
Expanding the Range of Convergence of the CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(1), pp. 13-21, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
coordinate rotational digital computer, range of convergence, numerical values, functional arguments, fixed-point hardware implementation, iterative methods, digital arithmetic, roundoff errors, CORDIC algorithm |
33 | Mario Garrido, Petter Kallstrom, Martin Kumm, Oscar Gustafsson |
CORDIC II: A New Improved CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(2), pp. 186-190, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
33 | Tushar Supe, David Anderson |
Super-CORDIC: An approximation based parallel and redundant CORDIC algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2016, Phuket, Thailand, October 24-27, 2016, pp. 1-5, 2016, IEEE, 978-1-5090-0629-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
33 | Hongzhi Wang 0003 |
Architectures reconfigurables à base d'opérateur CORDIC pour le traitement du signal: Applications aux récepteurs MIMO. (Reconfigurable architecture based on CORDIC opérator for signal processing: Applications to MIMO receivers). ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2009 |
RDF |
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