Search results for "Carry-free"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Behrooz Parhami	Carry-Free Addition of Recorded Binary Signed-Digit Numbers.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	string recoding, recoded binary signed-digit numbers, number representation systems, borrow chains, propagation-free addition, signed-digit arithmetic, limited-carry propagation, binary signed-digit numbers, borrow-free subtraction, digital arithmetic, subtraction, annihilation, Carry-free addition, carry-free addition, signed digit number representation
61	Parag K. Lala, Alvernon Walker	On-Line Error Detectable Carry-Free Adder Design.	DFT	2001	DBLP DOI BibTeX RDF	carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection
60	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-testable carry-free divider.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
59	Syed Mahfuzul Aziz, S. J. Carr	On C-Testability of Carry Free Dividers.	DELTA	2002	DBLP DOI BibTeX RDF	Carry-free, C-Testability, Divider, Radix-2
32	Erkay Savas	A Carry-Free Architecture for Montgomery Inversion.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Montgomery inversion, redundant signed representation, elliptic curve cryptography
30	Yuji Ohi, Takafumi Aoki, Tatsuo Higuchi 0001	Redundant Complex Number Systems.	ISMVL	1995	DBLP DOI BibTeX RDF	redundant complex number systems, complex number representations, high-speed arithmetic circuits, positional number system, binary-tree multiple-operand addition, arithmetic algorithms, redundant number systems, carry-free addition
30	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
27	John Moskal, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Palash Sarkar 0001, Bimal K. Roy, Pabitra Pal Choudhury	VLSI Implementation of Modulo Multiplication Using Carry Free Addition.	VLSI Design	1997	DBLP DOI BibTeX RDF
27	Chin-Long Wey	Built-in self-test (BIST) design of high-speed carry-free dividers.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
23	Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi	An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition
23	Sorin Cotofana, Stamatis Vassiliadis	Signed Digit Addition and Related Operations with Threshold Logic.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation
23	Behrooz Parhami	Comments on "Evaluation of A + B + K Conditions Without Carry Propagation".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	carry-free circuit, A+B=K, negative effects, carry-save redundant numbers, (3, 2)-counters, carry propagation, carry-save numbers, pipeline processing, logic circuits, pipelined architectures, comparators, addition, parallel counters, redundant number representation, conditional branches
23	Jean Duprat, Yvan Herreros, Sylvanus Kla	New Redundant Representations of Complex Numbers and Vectors.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	n-dimensional vectors, digital arithmetic, multiplication, redundant representation, complex numbers, carry-free addition, signed-digit number systems, polygonal representation
23	Behrooz Parhami	On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	zero detection, arithmetic support functions, generalized signed-digit number systems, OSD number representation, borrow-free subtraction, overflow handling, digital arithmetic, redundant number representations, carry-free addition, sign detection
22	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.	DFT	2003	DBLP DOI BibTeX RDF
20	Baofeng Qi, Shaojiang Sun, Yihui Tong, Jie Zhang, Zhehe Wang, Xianchao Wang	Algorithm-based Study on Transformation Combination for Carry-free Modified Signed Digit(MSD) Addition.	CSCloud/EdgeCom	2023	DBLP DOI BibTeX RDF
20	Yunfu Shen, Wang Zhehe, Junjie Peng, Shan Ouyang 0003	Characteristics of Parallel Carry-Free Three-Step MSD Additions.	IEEE Access	2021	DBLP DOI BibTeX RDF
20	John Reuben, Dietmar Fey	Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles.	ISVLSI	2021	DBLP DOI BibTeX RDF
20	Shengqi Yu, Ahmed Soltan, Rishad A. Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo, Alex Yakovlev	Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.	DATE	2020	DBLP DOI BibTeX RDF
20	Junjie Peng, Shuai Kong, Chao Ye	A Carry-Free Multiplication Implementation Method.	IEEE Access	2019	DBLP DOI BibTeX RDF
20	Ayan Palchaudhuri, Anindya Sundar Dhar	Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs.	HiPC	2017	DBLP DOI BibTeX RDF
20	Wen Yan, Milos D. Ercegovac	Radix-4 energy efficient carry-free truncated multiplier.	ACSSC	2016	DBLP DOI BibTeX RDF
20	Klaus Schneider 0001, Adrian Willenbücher	A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers.	FCCM	2014	DBLP DOI BibTeX RDF
20	Se Yong Park, Gireeja Ranade, Anant Sahai	Carry-free models and beyond.	ISIT	2012	DBLP DOI BibTeX RDF
20	J. M. Pierre Langlois, Dhamin Al-Khalili	Carry-free approximate squaring functions with O(n) complexity and O(1) delay.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
20	Tso-Bing Juang, Shen-Fu Hsiao	Low-error carry-free fixed-width multipliers with low-cost compensation circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2005	DBLP DOI BibTeX RDF
20	Wolfgang Rülling	A remark on carry-free binary multiplication.	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
20	Milos D. Ercegovac, Tomás Lang, Y. Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig	Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm".	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
20	Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig	Correction to "A carry-free 54 b x 54 b multiplier using equivalent bit conversion algorithm".	IEEE J. Solid State Circuits	2003	DBLP DOI BibTeX RDF
20	Shao-Hui Shieh, Cheng-Wen Wu	Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition.	J. Inf. Sci. Eng.	2003	DBLP BibTeX RDF
20	Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala	On-line Error Detection in a Carry-free Adder.	IWLS	2002	DBLP BibTeX RDF
20	Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig	A carry-free 54b×54b multiplier using equivalent bit conversion algorithm.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
20	Jen-Shiun Chiang, Hung-Da Chung, Ming-Hsou Tsai	A radix-2 general division algorithm with carry-free scheme and the divider implementation.	ICECS	1999	DBLP DOI BibTeX RDF
20	Hsiang-Feng Chi	A high-speed RSD adaptive filter architecture with a fast carry-free SPT converter.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
20	Gianluca Cena, Paolo Montuschi, Luigi Ciminiera, Andrea Sanna	A Q-Coder Algorithm with Carry Free Addition.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	image compression, arithmetic coding
20	Chin-Long Wey	Built-In Self Test (BIST) Design of High-Speed Carry-Free Dividers.	ISCAS	1995	DBLP DOI BibTeX RDF
20	Chin-Long Wey	Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data.	ICCD	1994	DBLP DOI BibTeX RDF
20	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-Testable Carry-Free Divider.	ICCD	1993	DBLP DOI BibTeX RDF
20	David Y. Y. Yun, Chang Nian Zhang	A fast carry-free algorithm and hardware design for extended integer GCD computation.	SYMSAC	1986	DBLP DOI BibTeX RDF
19	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Fault tolerance, error checking, high-speed arithmetic
19	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.	IOLTS	2004	DBLP DOI BibTeX RDF
14	Fekri Kharbash, Ghulam M. Chaudhry	Reliable Binary Signed Digit Number Adder Design.	ISVLSI	2007	DBLP DOI BibTeX RDF
12	Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002	An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	number comparison, sign determination, overflow detection, VLSI, RNS, parity check
12	Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme	Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
12	Sung-Ho Baik, Kyung-Nam Han, E. Yoon	A 230 MHz 8 tap programmable FIR filter using redundant binary number system.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
12	Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Digit On-line Large Radix CORDIC Rotator.	ASAP	1995	DBLP DOI BibTeX RDF	Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm
12	André Vandermeulebroecke, Etienne Vanzieleghem, Tony Denayer, Paul G. A. Jespers	A Single Chip 1024 Bits RSA Processor.	EUROCRYPT	1989	DBLP DOI BibTeX RDF
7	Jeff Rebacz, Erdal Oruklu, Jafar Saniie	High performance signed-digit decimal adders.	EIT	2009	DBLP DOI BibTeX RDF
7	Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi	RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX.	VTC Spring	2008	DBLP DOI BibTeX RDF
7	Pedro Miguens Matutino, Leonel Sousa	An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences.	DSD	2008	DBLP DOI BibTeX RDF
7	Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi	Dual-mode RNS based programmable decimation filter for WCDMA and WLANa.	ISCAS	2008	DBLP DOI BibTeX RDF
7	Luigi Dadda	Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware design, decimal arithmetic
7	Leonel Sousa	Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
7	Tiago Dias 0001, Nuno Roma, Leonel Sousa	Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators.	PATMOS	2006	DBLP DOI BibTeX RDF
7	Henning Gundersen, Yngvar Berg	A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices.	ISMVL	2006	DBLP DOI BibTeX RDF
7	Daniel H.-Y. Teng	A Novel Current-Mode Cmos Multiple-Valued Logic Neuron.	CCECE	2006	DBLP DOI BibTeX RDF
7	Xinyu Guo, Carl Sechen	High Speed Redundant Adder and Divider in Output Prediction Logic.	ISVLSI	2005	DBLP DOI BibTeX RDF
7	Andreas Lindahl, Lars Bengtsson	A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation.	DSD	2005	DBLP DOI BibTeX RDF
7	José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera	Algorithm and Architecture for Logarithm, Exponential, and Powering Computation.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
7	Wu Woan Kim, Sang-Dong Jang	Multiplier with Parallel CSA Using CRT's Specific Moduli (2k-1, 2k , 2k+1).	ICCSA (2)	2004	DBLP DOI BibTeX RDF
7	Behrooz Parhami	Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division
7	Jen-Shiun Chiang, Min-Shiou Tsai	A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system
7	Hossam A. H. Fahmy, Michael J. Flynn	The Case for a Redundant Format in Floating Point Arithmetic.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
7	José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera	High-Radix Iterative Algorithm for Powering Computation.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
7	Aryan Saed, Majid Ahmadi, Graham A. Jullien	A Number System with Continuous Valued Digits and Modulo Arithmetic.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	continuous digits, modulo arithmetic, low-noise circuitry, Computer arithmetic, multiple-valued logic
7	Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. S. Swamy	An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
7	Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli	Fast Radix-4 Retimed Division with Selection by Comparisons.	ASAP	2002	DBLP DOI BibTeX RDF
7	Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup	Modular Multiplication and Base Extensions in Residue Number Systems.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
7	Aryan Saed, Majid Ahmadi, Graham A. Jullien	Arithmetic with Signed Analog Digits.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
7	Miguel A. Sacristán, María Victoria Rodellar Biarge, Antonio Diaz, V. Garcia, Pedro Gómez 0001	A Reusable Inner Product Unit for DSP Applications.	EUROMICRO	1999	DBLP DOI BibTeX RDF
7	Shugang Wei, Kensuke Shimizu	Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
7	Alexander Skavantzos	An Efficient Residue to Weighted Converter for a New Residue Number System.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF
7	Karl C. Posch, Reinhard Posch	Modulo Reduction in Residue Number Systems.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF
7	Luigi Dadda	A polyphase architecture for serial-input convolvers.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF