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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 69 occurrences of 51 keywords
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Results
Found 75 publication records. Showing 75 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
65 | Behrooz Parhami |
Carry-Free Addition of Recorded Binary Signed-Digit Numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 37(11), pp. 1470-1476, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
string recoding, recoded binary signed-digit numbers, number representation systems, borrow chains, propagation-free addition, signed-digit arithmetic, limited-carry propagation, binary signed-digit numbers, borrow-free subtraction, digital arithmetic, subtraction, annihilation, Carry-free addition, carry-free addition, signed digit number representation |
61 | Parag K. Lala, Alvernon Walker |
On-Line Error Detectable Carry-Free Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 66-71, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection |
60 | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi |
A C-testable carry-free divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(4), pp. 472-488, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
59 | Syed Mahfuzul Aziz, S. J. Carr |
On C-Testability of Carry Free Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 417-424, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Carry-free, C-Testability, Divider, Radix-2 |
32 | Erkay Savas |
A Carry-Free Architecture for Montgomery Inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(12), pp. 1508-1519, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Montgomery inversion, redundant signed representation, elliptic curve cryptography |
30 | Yuji Ohi, Takafumi Aoki, Tatsuo Higuchi 0001 |
Redundant Complex Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 14-19, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
redundant complex number systems, complex number representations, high-speed arithmetic circuits, positional number system, binary-tree multiple-operand addition, arithmetic algorithms, redundant number systems, carry-free addition |
30 | W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi |
A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 398-402, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron |
27 | John Moskal, Erdal Oruklu, Jafar Saniie |
Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1089-1092, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Palash Sarkar 0001, Bimal K. Roy, Pabitra Pal Choudhury |
VLSI Implementation of Modulo Multiplication Using Carry Free Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 457-460, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
27 | Chin-Long Wey |
Built-in self-test (BIST) design of high-speed carry-free dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(1), pp. 141-145, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
23 | Ghassem Jaberipur, Behrooz Parhami, Mohammad Ghodsi |
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 42(2), pp. 149-158, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
(4,2)-compressor, digit set, signed digit, computer arithmetic, redundant number system, carry-free addition |
23 | Sorin Cotofana, Stamatis Vassiliadis |
Signed Digit Addition and Related Operations with Threshold Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 193-207, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
signed-digit arithmetic, redundant adders, redundant multipliers, neural networks, Computer arithmetic, threshold logic, carry-free addition, signed-digit number representation |
23 | Behrooz Parhami |
Comments on "Evaluation of A + B + K Conditions Without Carry Propagation". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(3), pp. 381, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
carry-free circuit, A+B=K, negative effects, carry-save redundant numbers, (3, 2)-counters, carry propagation, carry-save numbers, pipeline processing, logic circuits, pipelined architectures, comparators, addition, parallel counters, redundant number representation, conditional branches |
23 | Jean Duprat, Yvan Herreros, Sylvanus Kla |
New Redundant Representations of Complex Numbers and Vectors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 817-824, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
n-dimensional vectors, digital arithmetic, multiplication, redundant representation, complex numbers, carry-free addition, signed-digit number systems, polygonal representation |
23 | Behrooz Parhami |
On the Implementation of Arithmetic Support Functions for Generalized Signed-Digit Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(3), pp. 379-384, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
zero detection, arithmetic support functions, generalized signed-digit number systems, OSD number representation, borrow-free subtraction, overflow handling, digital arithmetic, redundant number representations, carry-free addition, sign detection |
22 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 401-408, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Baofeng Qi, Shaojiang Sun, Yihui Tong, Jie Zhang, Zhehe Wang, Xianchao Wang |
Algorithm-based Study on Transformation Combination for Carry-free Modified Signed Digit(MSD) Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSCloud/EdgeCom ![In: 10th IEEE International Conference on Cyber Security and Cloud Computing, CSCloud 2023 / IEEE 9th International Conference on Edge Computing and Scalable Cloud, EdgeCom 2023, Xiangtan, Hunan, China, July 1-3, 2023, pp. 298-304, 2023, IEEE, 979-8-3503-1246-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Yunfu Shen, Wang Zhehe, Junjie Peng, Shan Ouyang 0003 |
Characteristics of Parallel Carry-Free Three-Step MSD Additions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 49601-49613, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | John Reuben, Dietmar Fey |
Carry-free Addition in Resistive RAM Array: n-bit Addition in 22 Memory Cycles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2021, Tampa, FL, USA, July 7-9, 2021, pp. 157-163, 2021, IEEE, 978-1-6654-3946-6. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
20 | Shengqi Yu, Ahmed Soltan, Rishad A. Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo, Alex Yakovlev |
Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, pp. 638-641, 2020, IEEE, 978-3-9819263-4-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
20 | Junjie Peng, Shuai Kong, Chao Ye |
A Carry-Free Multiplication Implementation Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 85848-85854, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
20 | Ayan Palchaudhuri, Anindya Sundar Dhar |
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: 24th IEEE International Conference on High Performance Computing, HiPC 2017, Jaipur, India, December 18-21, 2017, pp. 104-113, 2017, IEEE Computer Society, 978-1-5386-2293-3. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
20 | Wen Yan, Milos D. Ercegovac |
Radix-4 energy efficient carry-free truncated multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSSC ![In: 50th Asilomar Conference on Signals, Systems and Computers, ACSSC 2016, Pacific Grove, CA, USA, November 6-9, 2016, pp. 1596-1600, 2016, IEEE, 978-1-5386-3954-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
20 | Klaus Schneider 0001, Adrian Willenbücher |
A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014, pp. 44-51, 2014, IEEE Computer Society, 978-1-4799-5110-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
20 | Se Yong Park, Gireeja Ranade, Anant Sahai |
Carry-free models and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIT ![In: Proceedings of the 2012 IEEE International Symposium on Information Theory, ISIT 2012, Cambridge, MA, USA, July 1-6, 2012, pp. 1927-1931, 2012, IEEE, 978-1-4673-2580-6. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
20 | J. M. Pierre Langlois, Dhamin Al-Khalili |
Carry-free approximate squaring functions with O(n) complexity and O(1) delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(5), pp. 374-378, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Tso-Bing Juang, Shen-Fu Hsiao |
Low-error carry-free fixed-width multipliers with low-cost compensation circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 52-II(6), pp. 299-303, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Wolfgang Rülling |
A remark on carry-free binary multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(1), pp. 159-160, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Milos D. Ercegovac, Tomás Lang, Y. Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig |
Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(1), pp. 160-161, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig |
Correction to "A carry-free 54 b x 54 b multiplier using equivalent bit conversion algorithm". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 38(1), pp. 159, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Shao-Hui Shieh, Cheng-Wen Wu |
Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Sci. Eng. ![In: J. Inf. Sci. Eng. 19(6), pp. 1015-1039, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
20 | Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala |
On-line Error Detection in a Carry-free Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWLS ![In: 11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA., pp. 251-254, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
20 | Yun Kim, Bang-Sup Song, John Grosspietsch, Steven F. Gillig |
A carry-free 54b×54b multiplier using equivalent bit conversion algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(10), pp. 1538-1545, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Jen-Shiun Chiang, Hung-Da Chung, Ming-Hsou Tsai |
A radix-2 general division algorithm with carry-free scheme and the divider implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 569-572, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Hsiang-Feng Chi |
A high-speed RSD adaptive filter architecture with a fast carry-free SPT converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 187-190, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Gianluca Cena, Paolo Montuschi, Luigi Ciminiera, Andrea Sanna |
A Q-Coder Algorithm with Carry Free Addition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 282-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
image compression, arithmetic coding |
20 | Chin-Long Wey |
Built-In Self Test (BIST) Design of High-Speed Carry-Free Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30 - May 3, 1995, pp. 1916-1919, 1995, IEEE, 0-7803-2570-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
20 | Chin-Long Wey |
Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 124-127, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
20 | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi |
A C-Testable Carry-Free Divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 206-213, 1993, IEEE Computer Society, 0-8186-4230-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
20 | David Y. Y. Yun, Chang Nian Zhang |
A fast carry-free algorithm and hardware design for extended integer GCD computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYMSAC ![In: Proceedings of the Symposium on Symbolic and Algebraic Manipulation, SYMSAC 1986, Waterloo, Ontario, Canada, July 21-23, 1986, pp. 82-84, 1986, ACM, 0-89791-199-7. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 534-540, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Fault tolerance, error checking, high-speed arithmetic |
19 | Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano |
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 141-148, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
14 | Fekri Kharbash, Ghulam M. Chaudhry |
Reliable Binary Signed Digit Number Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 479-484, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
12 | Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002 |
An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(10), pp. 1563-1571, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
number comparison, sign determination, overflow detection, VLSI, RNS, parity check |
12 | Shen-Fu Hsiao, Chun-Yi Lau, Jean-Marc Delosme |
Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(2), pp. 155-166, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
12 | Sung-Ho Baik, Kyung-Nam Han, E. Yoon |
A 230 MHz 8 tap programmable FIR filter using redundant binary number system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 415-418, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
12 | Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata |
Digit On-line Large Radix CORDIC Rotator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France, pp. 246-257, 1995, IEEE Computer Society, 0-8186-7109-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm |
12 | André Vandermeulebroecke, Etienne Vanzieleghem, Tony Denayer, Paul G. A. Jespers |
A Single Chip 1024 Bits RSA Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '89, Workshop on the Theory and Application of of Cryptographic Techniques, Houthalen, Belgium, April 10-13, 1989, Proceedings, pp. 219-236, 1989, Springer, 3-540-53433-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
7 | Jeff Rebacz, Erdal Oruklu, Jafar Saniie |
High performance signed-digit decimal adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2009 IEEE International Conference on Electro/Information Technology, EIT 2009, Windsor, Ontario, Canada, June 7-9, 2009, pp. 251-255, 2009, IEEE, 978-1-4244-3355-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
7 | Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi |
RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 67th IEEE Vehicular Technology Conference, VTC Spring 2008, 11-14 May 2008, Singapore, pp. 1831-1835, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Pedro Miguens Matutino, Leonel Sousa |
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 768-775, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi |
Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 952-955, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
7 | Luigi Dadda |
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1320-1328, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multioperand adders, Computer arithmetic, hardware design, decimal arithmetic |
7 | Leonel Sousa |
Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 240-250, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
7 | Tiago Dias 0001, Nuno Roma, Leonel Sousa |
Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 247-255, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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7 | Henning Gundersen, Yngvar Berg |
A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 18, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Daniel H.-Y. Teng |
A Novel Current-Mode Cmos Multiple-Valued Logic Neuron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1715-1718, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | Xinyu Guo, Carl Sechen |
High Speed Redundant Adder and Divider in Output Prediction Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 34-41, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | Andreas Lindahl, Lars Bengtsson |
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 42-47, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
7 | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera |
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(9), pp. 1085-1096, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Wu Woan Kim, Sang-Dong Jang |
Multiplier with Parallel CSA Using CRT's Specific Moduli (2k-1, 2k , 2k+1). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2004, International Conference, Assisi, Italy, May 14-17, 2004, Proceedings, Part II, pp. 216-225, 2004, Springer, 3-540-22056-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | Behrooz Parhami |
Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(11), pp. 1509-1514, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
digit-selector PLA, high-radix division, p-d plot, quotient digit selection, SRT division, Digit-recurrence division |
7 | Jen-Shiun Chiang, Min-Shiou Tsai |
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 117-124, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
floating-point division, new Svoboda-Tung division, radix-4, Svoboda-Tung division, computer arithmetic, prescaling, signed digit number system |
7 | Hossam A. H. Fahmy, Michael J. Flynn |
The Case for a Redundant Format in Floating Point Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 95-, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
7 | José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera |
High-Radix Iterative Algorithm for Powering Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 204-211, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
7 | Aryan Saed, Majid Ahmadi, Graham A. Jullien |
A Number System with Continuous Valued Digits and Modulo Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(11), pp. 1294-1305, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
continuous digits, modulo arithmetic, low-noise circuitry, Computer arithmetic, multiple-valued logic |
7 | Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. S. Swamy |
An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 763-766, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli |
Fast Radix-4 Retimed Division with Selection by Comparisons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 185-196, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Jean-Claude Bajard, Laurent-Stéphane Didier, Peter Kornerup |
Modular Multiplication and Base Extensions in Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 59-65, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
7 | Aryan Saed, Majid Ahmadi, Graham A. Jullien |
Arithmetic with Signed Analog Digits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia, pp. 134-141, 1999, IEEE Computer Society, 0-7695-0116-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
7 | Miguel A. Sacristán, María Victoria Rodellar Biarge, Antonio Diaz, V. Garcia, Pedro Gómez 0001 |
A Reusable Inner Product Unit for DSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1209-1213, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
7 | Shugang Wei, Kensuke Shimizu |
Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 4-6 March 1999, Ann Arbor, MI, USA, pp. 218-, 1999, IEEE Computer Society, 0-7695-0104-4. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
7 | Alexander Skavantzos |
An Efficient Residue to Weighted Converter for a New Residue Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 185-191, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
7 | Karl C. Posch, Reinhard Posch |
Modulo Reduction in Residue Number Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(5), pp. 449-454, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
7 | Luigi Dadda |
A polyphase architecture for serial-input convolvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 2(1), pp. 17-27, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
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