Search results for "CoreConnect"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
48	Glenn Leary, Krishna Mehta, Karam S. Chatha	Performance and resource optimization of NoC router architecture for master and slave IP cores.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	FPGA, network-on-chip
42	Nagu R. Dhanwada, Reinaldo A. Bergamaschi, William W. Dungan, Indira Nair, Paul Gramann, William E. Dougherty, Ing-Chao Lin	Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems.	Des. Autom. Embed. Syst.	2005	DBLP DOI BibTeX RDF
42	Amit Goel, William R. Lee	Formal verification of an IBM CoreConnect processor local bus arbiter core.	DAC	2000	DBLP DOI BibTeX RDF
33	Yafang Wang, Cheng Zhang, Yanli Hou, Boning Hu	Implementation of Gigabit Ethernet Network Based on SOPC.	APWCS	2010	DBLP DOI BibTeX RDF	FGPA, coreConnect, PLB-Link, VxWorks, SOPC
33	Nagu R. Dhanwada, Ing-Chao Lin, Vijaykrishnan Narayanan	A power estimation methodology for systemC transaction level models.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	CoreConnect, systemC, power analysis, transaction level models, PowerPC
24	Douglas Densmore, Adam Donlin, Alberto L. Sangiovanni-Vincentelli	FPGA architecture characterization for system level performance analysis.	DATE	2006	DBLP DOI BibTeX RDF
24	Fabrizio Ferrandi, Giovanna Ferrara, Roberto Palazzo, Vincenzo Rana, Marco D. Santambrogio	VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow.	IPDPS	2006	DBLP DOI BibTeX RDF
24	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
24	Kyeong Keol Ryu, Vincent John Mooney	Automated Bus Generation for Multiprocessor SoC Design.	DATE	2003	DBLP DOI BibTeX RDF
24	Satnam Singh	Interface specification for reconfigurable components.	ICCAD	2002	DBLP DOI BibTeX RDF
24	Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III	A Comparison of Five Different Multiprocessor SoC Bus Architectures.	DSD	2001	DBLP DOI BibTeX RDF

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