Search results for "DTMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
134	Zhiyuan Li, Mingyan Yu, Jianguo Ma	A Novel Input Stage Based on DTMOS for Low-Voltage Low-Noise Operational Amplifier.	APCCAS	2006	DBLP DOI BibTeX RDF
112	E. Shen, J. B. Kuo	0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
70	Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul	Robust ultra-low power sub-threshold DTMOS logic.	ISLPED	2000	DBLP DOI BibTeX RDF
64	Abhisek Dixit, V. Ramgopal Rao	A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime.	VLSI Design	2003	DBLP DOI BibTeX RDF
49	Mohammad Maymandi-Nejad, Manoj Sachdev	DTMOS Technique for Low-Voltage Analog Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
49	Mohammad Maymandi-Nejad, Manoj Sachdev	A 0.8V Delta-Sigma modulator using DTMOS technique.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
42	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	FPGA	2004	DBLP DOI BibTeX RDF
42	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
36	Yiming Li 0005, S. M. Sze, Tien-Sheng Chao	A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation.	Eng. Comput.	2002	DBLP DOI BibTeX RDF	DTMOS, Dynamic domain decomposition, Parallel I-V points calculation, VLSI device simulation, Load balancing, MOSFET, Linux cluster
28	Pushkar Srivastava, Ravindra Kumar Sharma, Rahul Kumar Gupta, Firat Kaçar, Rajeev Kumar Ranjan 0002	New DTMOS Based High Frequency Memristor Emulator and Its Nonlinear Applications.	IEEE Access	2024	DBLP DOI BibTeX RDF
28	Arvin Kumar, Shweta Kumari, Maneesha Gupta, Harish Parthasarathy	A New Low-Voltage Second Generation Voltage Conveyor Using Merged Voltage Follower and DTMOS Techniques.	J. Circuits Syst. Comput.	2024	DBLP DOI BibTeX RDF
28	Annu Dabas, Shweta Kumari, Maneesha Gupta, Richa Yadav	Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique.	Integr.	2023	DBLP DOI BibTeX RDF
28	Ananda Y. R., Nehal Raj, Gaurav Trivedi	A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
28	Om Krishna Gupta, Neeta Pandey, Maneesha Gupta	Refining RNMC compensation for Three Stage Amplifier using DTMOS Transistor and FFVF.	ICCCNT	2023	DBLP DOI BibTeX RDF
28	Mihika Mahendra, Shweta Kumari, Maneesha Gupta	Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application.	Integr.	2022	DBLP DOI BibTeX RDF
28	Ersin Alaybeyoglu, Deniz Özenli	Operational Amplifier Design Employing DTMOS Technique with Dual Supply Voltages.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
28	Tao He, Qi Han, Yu Li, Peng Yuan, Huixiang Huang	A Low Power Operational Amplifier Design Based on SOI DTMOS.	EITCE	2022	DBLP DOI BibTeX RDF
28	Mihika Mahendra, Shweta Kumari, Maneesha Gupta, Ankur Sangal	Low voltage high performance super class AB OTA design using SCCM and DTMOS with enhanced slew rate and DC gain.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
28	Ankush Chunn, Akshay Agrawal, Alok Naugarhiya	An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times.	VDAT	2020	DBLP DOI BibTeX RDF
28	Purnima Kalekar, Prasad Vernekar, M. H. Vasantha, Y. B. Nithin Kumar, Edoardo Bonizzoni	A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications.	IEEE SENSORS	2018	DBLP DOI BibTeX RDF
28	Ankit Chaudhary	A Low Power DTMOS Based Modified Current Mirror for Improved Bandwidth Using Resistive Compensation Technique.	ICCCNT	2018	DBLP DOI BibTeX RDF
28	Niharika Narang, Bhawna Aggarwal, Maneesha Gupta	DTMOS and FD-FVF based low voltage high performance Voltage Differencing Transconductance Amplifier (VDTA) and its application in MISO filter.	Microelectron. J.	2017	DBLP DOI BibTeX RDF
28	Ying-Khai Teh, Philip K. T. Mok	DTMOS-Based Pulse Transformer Boost Converter With Complementary Charge Pump for Multisource Energy Harvesting.	IEEE Trans. Circuits Syst. II Express Briefs	2016	DBLP DOI BibTeX RDF
28	Niharika Narang, Bhawna Aggarwal, Maneesha Gupta	DTMOS based low voltage high performance FVF-OTA and its application in MISO filter.	ICACCI	2016	DBLP DOI BibTeX RDF
28	Maria Glória Caño de Andrade, João Antonio Martino, Marc Aoulaiche, Nadine Collaert, Eddy Simoen, Cor Claeys	Investigation of Bulk and DTMOS triple-gate devices under 60 MeV proton irradiation.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
28	Shailesh Singh Chouhan, Kari Halonen	The design and implementation of DTMOS biased all PMOS rectifier for RF energy harvesting.	NEWCAS	2014	DBLP DOI BibTeX RDF
28	Joana Correia, Nuno Mancelos, João Goes	Stability Improvements in a Rail-to-Rail Input/Output, Constant Gm Operational Amplifier, at 0.4 V Operation, Using the Low-Voltage DTMOS Technique.	DoCEIS	2014	DBLP DOI BibTeX RDF
28	Jiaxin Liu, Yu Han, Liangbo Xie, Yao Wang, Guangjun Wen	A 1-V DTMOS-Based fully differential telescopic OTA.	APCCAS	2014	DBLP DOI BibTeX RDF
28	KyungSoo Kim, Wansoo Nah, SoYoung Kim	Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits.	EMC Compo	2013	DBLP DOI BibTeX RDF
28	Shailesh Singh Chouhan, Kari Halonen	The DTMOS based UHF RF to DC conversion.	ICECS	2013	DBLP DOI BibTeX RDF
28	Atilla Uygur, Hakan Kuntman	0.4V OTA design using DTMOS transistors for EEG data processing.	SIU	2013	DBLP DOI BibTeX RDF
28	Ehsan Kargaran, Mohamad Sawan, Khalil Mafinezhad, Hooman Nabovati	Design of 0.4V, 386nW OTA using DTMOS technique for biomedical applications.	MWSCAS	2012	DBLP DOI BibTeX RDF
28	Deepak Kumar, Pankaj Kumar, Manisha Pattanaik	Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design.	SBCCI	2010	DBLP DOI BibTeX RDF
28	Chih-Hsiang Lin, James B. Kuo	Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications.	ISCAS	2010	DBLP DOI BibTeX RDF
28	Abdul Kadir Kureshi, Mohd. Hasan	DTMOS Based Low Power High Speed Interconnects for FPGA.	J. Comput.	2009	DBLP BibTeX RDF
28	Chih-Hsiang Lin, James B. Kuo	Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.	PATMOS	2009	DBLP DOI BibTeX RDF
28	Myeong-Eun Hwang, Kaushik Roy 0001	A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology.	CICC	2008	DBLP DOI BibTeX RDF
28	Hervé F. Achigui, Christian Jesús B. Fayomi, Mohamad Sawan	1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
28	Hervé F. Achigui, Christian Jesús B. Fayomi, Mohamad Sawan	A DTMOS-based 1 V opamp.	ICECS	2003	DBLP DOI BibTeX RDF
28	S. C. Liu, F. A. Wu, James B. Kuo	A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
21	Walid Elgharbawy, Pradeep Golconda, Ashok Kumar 0001, Magdy A. Bayoumi	A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
21	James B. Kuo	Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SoC Applications, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
21	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
21	Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek	Low energy FPGA interconnect design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	FPGA, low power, interconnect, encoding
21	Geun Rae Cho, Tom Chen 0001	Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic.	ISQED	2003	DBLP DOI BibTeX RDF
21	Hendrawan Soeleman, Kaushik Roy 0001, Bipul Chandra Paul	Robust subthreshold logic for ultra-low power operation.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF