Search results for "DWT/IDWT"

Found 11 publication records. Showing 11 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
120	Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin	Low-Power Multiplierless 2-D DWT and IDWT Architectures Using 4-tap Daubechies Filters.	PDCAT	2006	DBLP DOI BibTeX RDF	DWT/IDWT, image coding/decoding system, 4-tap Daubechies filters, multiplierless, low-power, JPEG-2000
120	Robert Michael Owens, Mohan Vishwanath	A Very Efficient Storage Structure for DWT and IDWT Filters.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
120	Mohan Vishwanath, Robert Michael Owens	A Common Architecture For The DWT and IDWT.	ASAP	1996	DBLP DOI BibTeX RDF	inverse discrete wavelet transform, j'th octave, wavelet transforms, discrete wavelet transform, digital signal processing chips, filter bank, single chip
116	Leibo Liu, Xuejin Wang, Hongying Meng, Li Zhang 0023, Zhihua Wang 0001, Hongyi Chen	A VLSI architecture of spatial combinative lifting algorithm based 2-D DWT/IDWT.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
98	Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen	Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
98	Kavish Seth, S. Srinivasan 0001	VLSI Implementation of 2-D DWT/IDWT Cores Using 9/7-Tap Filter Banks Based on the Non-Expansive Symmetric Extension Scheme.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	2D-DWT/IDWT Hardware, Non-expansive symmetric Extension, Canonic Signed Digit Arithmetic, Sub-expression Sharing, Low Power
58	Patrizio Campisi, Alessandro Neri 0001	Video watermarking in the 3D-DWT domain using perceptual masking.	ICIP (1)	2005	DBLP DOI BibTeX RDF
46	S. S. Divakara, Sudarshan Patilkulkarni, Cyril Prasanna Raj	Novel DWT/IDWT Architecture for 3D with Nine Stage 2D Parallel Processing using Split Distributed Arithmetic.	Int. J. Image Graph.	2020	DBLP DOI BibTeX RDF
46	Kalaivani Ramanathan, N. J. R. Muniraj	DWT-IDWT-based MB-OFDM UWB with digital down converter and digital up converter for power line communication in the frequency band of 50 to 578 MHz.	Ann. des Télécommunications	2015	DBLP DOI BibTeX RDF
46	Amit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi, Steve R. Gunn	Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry.	IEEE Trans. Circuits Syst. II Express Briefs	2009	DBLP DOI BibTeX RDF
30	Hannu Olkkonen, Juuso T. Olkkonen	Simplified biorthogonal discrete wavelet transform for VLSI architecture design.	Signal Image Video Process.	2008	DBLP DOI BibTeX RDF	Biorthogonal discrete wavelet transform, VLSI, Lifting scheme