Search results for "FGPA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
64	Muhammad Riaz Sial	FGPA based cryptography computation platform and the basis conversion in composite finite fields ; FGPA tabanlı kriptografi işlem platformu ve bileşik sonlu cisimlerde baz dönüşümü. (PDF / PS)		2013	RDF
32	Bhargav Gokalgandhi, Prasanthi Maddala, Ivan Seskar	Implementation of FGPA based Channel Sounder for Large scale antenna systems using RFNoC on USRP Platform.	CoRR	2022	DBLP BibTeX RDF
32	Moslem Heidarpur, Mitra Mirhassani	An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
32	Chunhua Xiao, Dandan Xu, Shi Qiu, Chen Shi, Kun Ning	FGPA: Fine-Grained Pipelined Acceleration for Depthwise Separable CNN in Resource Constraint Scenarios.	ISPA/BDCloud/SocialCom/SustainCom	2021	DBLP DOI BibTeX RDF
32	Ahmed A. Hussain, Nizar Tayem, Abdel-Hamid Soliman	LDL Decomposition-based FGPA Real-time Implementation of DOA Estimation.	ACSSC	2018	DBLP DOI BibTeX RDF
32	Gaël Deest	Implementation Trade-Offs for FGPA accelerators . (Compromis d'implémentation pour accélérateurs FPGA).		2017	RDF
32	Tassadaq Hussain, Saqib Amin, Usman Zabit, Faysal Kamran, Olivier D. Bernal, Thierry Bosch	A High Performance Real-Time FGPA-Based Interferometry Sensor Architecture.	FIT	2016	DBLP DOI BibTeX RDF
32	Gerardo Marcos Tornez-Xavier, Felipe Gomez-Castañeda, Jose A. Moreno-Cadenas, Luis M. Flores-Nava	FGPA development and implementation of a solar panel emulator.	CCE	2013	DBLP DOI BibTeX RDF
32	R. Uma, P. Dhavachelvan	Performance enhancement for variable block optimization in FGPA synthesis process.	CCSEIT	2012	DBLP DOI BibTeX RDF
32	Wisnu Jatmiko, Petrus Mursanto, Andreas Febrian, M. Fajar, W. T. Anggoro, R. S. Rambe, Muhammad Iqbal Tawakal, Fauzi F. Jovan, M. Eka S.	Arrhythmia classification from wavelet feature on FGPA.	MHS	2011	DBLP DOI BibTeX RDF
32	Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros	Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks.	FPL	2011	DBLP DOI BibTeX RDF
32	Ulas Yaman, Melik Dolen, A. Bugra Koku	A novel command generation method with variable feedrate utilizing FGPA for motor drives.	WISES	2010	DBLP DOI BibTeX RDF
32	Zahir Larabi, Linlin Zhang, Virginie Fresse, Anne-Claire Legrand	Rapid prototyping of image analysis algorithms on an adaptive FGPA architecture.	EUSIPCO	2007	DBLP BibTeX RDF
32	Carol A. Fields	Creating hierarchy in HDL-based high density FGPA design.	EURO-DAC	1995	DBLP DOI BibTeX RDF
29	Yafang Wang, Cheng Zhang, Yanli Hou, Boning Hu	Implementation of Gigabit Ethernet Network Based on SOPC.	APWCS	2010	DBLP DOI BibTeX RDF	FGPA, coreConnect, PLB-Link, VxWorks, SOPC
29	Xuan-Thang Vu, Nguyen Anh Duc, Trinh Anh Vu	16-QAM Transmitter and Receiver Design Based on FPGA.	DELTA	2010	DBLP DOI BibTeX RDF	FGPA design, Carrier Synchronization, Symbol Recovery, 16-QAM Modulation
29	Ch. Rambabu, I. Chakrabarti	An Efficient Hillclimbing-based Watershed Algorithm and its Prototype Hardware Architecture.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	hillclimbing technique, FGPA implementation, image segmentation, watershed transformation
29	Herbert Walder, Christoph Steiger, Marco Platzner	Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing.	IPDPS	2003	DBLP DOI BibTeX RDF	FGPA, placement, task
23	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	FPGA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerators, fpga, caches
23	Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig	Performance and power of cache-based reconfigurable computing.	ISCA	2009	DBLP DOI BibTeX RDF	c-to-gates, c-to-hardware, co-processor accelerator, many-cache, synthesis compiler, fpga, caches
23	Renshen Wang, Evangeline F. Y. Young, Yi Zhu 0002, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng	3-D floorplanning using labeled tree and dual sequences.	ISPD	2008	DBLP DOI BibTeX RDF	3-D packing, sequence, labeled tree
23	Jason Cong	A new generation of C-base synthesis tool and domain-specific computing.	SoCC	2008	DBLP DOI BibTeX RDF
23	Che-Wei Lin, Jeen-Shing Wang, Chun-Chang Yu, Ting-Yu Chen	Synchronous Pipeline Circuit Design for an Adaptive Neuro-fuzzy Network.	ICIC (2)	2007	DBLP DOI BibTeX RDF	Synchronous pipeline design, neuro-fuzzy circuit, FPGA
23	Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan	Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.	DAC	2007	DBLP DOI BibTeX RDF
23	Eiji Nakamura, Shingo Asami, Tomoko Takahashi, Katsutoshi Sawada	Real Time Parameter Optimization for Elementary Motion Detectors.	ICIP	2006	DBLP DOI BibTeX RDF
23	Tom Van Court, Martin C. Herbordt	Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique.	FPL	2006	DBLP DOI BibTeX RDF
23	Hassan Hassan 0001, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry	Activity Packing in FPGAs for Leakage Power Reduction.	DATE	2005	DBLP DOI BibTeX RDF
23	Nazar Abbas Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez	Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core.	FPL	2003	DBLP DOI BibTeX RDF