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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10 occurrences of 9 keywords
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Results
Found 17 publication records. Showing 17 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
111 | Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja |
Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 162-167, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
102 | Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko |
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 141-146, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fixed polarity Reed-Muller expression, symmetric functions, MVL functions |
89 | Lun Li, Mitchell A. Thornton, Marek A. Perkowski |
A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 17-20 May 2006, Singapore, pp. 33, 2006, IEEE Computer Society, 0-7695-2532-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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80 | Yinshui Xia, B. Ali, A. E. A. Almaini |
Area and power optimization of FPRM function based circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 329-332, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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55 | Dragan Jankovic, Radomir S. Stankovic |
Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multiple-Valued Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 76-82, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
fixed polarity, FPRM, tabular technique, logic synthesis, multi-valued logic |
36 | Yichen Wang, Lunyao Wang |
Power optimization for FPRM logic using approximate computing technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, pp. 1-4, 2019, IEEE, 978-1-7281-0735-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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36 | Mingbo Wang, Pengjun Wang, Qiang Fu, Huihong Zhang |
Delay and area optimization for FPRM circuits based on MSPSO algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 379-382, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
36 | Apangshu Das, Sambhu Nath Pradhan |
Thermal aware FPRM based AND-XOR network synthesis of logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReTIS ![In: 2nd IEEE International Conference on Recent Trends in Information Systems, ReTIS 2015, Kolkata, India, July 9-11, 2015, pp. 497-502, 2015, IEEE, 978-1-4799-8349-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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36 | Fei Sun, Pengjun Wang, Haizhen Yu |
Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013, pp. 1-4, 2013, IEEE, 978-1-4673-6415-7. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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36 | Yinshui Xia, Xunwei Wu, A. E. A. Almaini |
Power Minimization of FPRM Functions Based on Polarity Conversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 18(3), pp. 325-331, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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33 | Rolf Drechsler, Michael Theobald, Bernd Becker 0001 |
Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 45(11), pp. 1294-1299, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
two-level AND/EXOR forms, FPRM, OFDD, minimization of FPRMs, Logic synthesis |
22 | Osnat Keren, Ilya Levin, Radomir S. Stankovic |
Use of gray decoding for implementation of symmetric functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 25-30, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Hafizur Rahaman 0001, Debesh K. Das |
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 172-177, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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22 | Bogdan J. Falkowski, Cicilia C. Lozano, Susanto Rahardja |
Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 177-183, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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22 | Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga |
Optimization of GF(4) Expressions Using the Extended Dual Polarity Property. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan, pp. 50-58, 2003, IEEE Computer Society, 0-7695-1918-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
quaternary function, GF(4) expression, dual polarity, optimization |
22 | Ugur Kalay, Douglas V. Hall, Marek A. Perkowski |
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 267-276, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set |
22 | Bogdan J. Falkowski, Chip-Hong Chang |
Optimization of partially-mixed-polarity Reed-Muller expansions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 383-386, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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