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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 19 occurrences of 12 keywords
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Results
Found 21 publication records. Showing 21 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
76 | Wei Hong II, Weikai Sun, Zhenhai Zhu, Hao Ji, Ben Song, Wayne Wei-Ming Dai |
A novel dimension reduction technique for the capacitance extraction of 3D VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 381-386, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
3D VLSI interconnects, DRT, Dimension Reduction Technique, FastCap, SPICELINK, dielectric layers, parallel signal lines, VLSI, capacitance extraction |
60 | Keith Nabors, Jacob K. White 0001 |
FastCap: a multipole accelerated 3-D capacitance extraction program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11), pp. 1447-1459, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
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60 | Weiping Shi, Jianguo Liu 0001, Naveen Kakani, Tiejun Yu |
A fast hierarchical algorithm for three-dimensional capacitanceextraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3), pp. 330-336, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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40 | Yanpei Liu, Guilherme Cox, Qingyuan Deng, Stark C. Draper, Ricardo Bianchini |
FastCap: An Efficient and Fair Algorithm for Power Capping in Many-Core Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1603.01313, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP BibTeX RDF |
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40 | Yanpei Liu, Guilherme Cox, Qingyuan Deng, Stark C. Draper, Ricardo Bianchini |
FastCap: An efficient and fair algorithm for power capping in many-core systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2016 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2016, Uppsala, Sweden, April 17-19, 2016, pp. 57-68, 2016, IEEE Computer Society, 978-1-5090-1953-3. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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40 | Shu Yan, Vivek Sarin, Weiping Shi |
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10), pp. 2282-2286, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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40 | Shu Yan, Vivek Sarin, Weiping Shi |
Sparse transformations and preconditioners for 3-D capacitance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1420-1426, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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40 | Joel R. Phillips, Jacob K. White 0001 |
A precorrected-FFT method for electrostatic analysis of complicated 3-D structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10), pp. 1059-1072, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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20 | Wenwen Chai, Dan Jiao, Cheng-Kok Koh |
A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 752-757, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
full wave, integral-equation-based methods, capacitance extraction, direct solver |
20 | Abinash Roy, Masud H. Chowdhury |
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2426-2429, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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20 | Nancy Ying Zhou, Zhuo Li 0001, Weiping Shi |
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 835-840, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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20 | Aditya Bansal, Bipul Chandra Paul, Kaushik Roy 0001 |
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2765-2774, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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20 | Michael D. Altman, Jaydeep P. Bardhan, Bruce Tidor, Jacob K. White 0001 |
FFTSVD: A Fast Multiscale Boundary-Element Method Solver Suitable for Bio-MEMS and Biomolecule Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(2), pp. 274-284, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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20 | Hao Gang Wang, Chi Hou Chan, Leung Tsang |
A new multilevel Green's function interpolation method for large-scale low-frequency EM simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1427-1443, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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20 | Dipanjan Gope, Vikram Jandhyala |
Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11), pp. 1575-1580, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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20 | Shu Yan, Vivek Sarin, Weiping Shi |
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 788-793, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect, iterative methods, preconditioning, capacitance extraction |
20 | Zhaozhi Yang, Zeyi Wang, Shuzhou Fang |
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 214-218, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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20 | Yanhong Yuan, Prithviraj Banerjee |
A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), Cancun, Mexico, May 1-5, 2000, pp. 323-330, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fast multipole algorithm, parallel algorithms, distributed memory multiprocessors, Capacitance extraction |
20 | Weiping Shi, Jianguo Liu 0001, Naveen Kakani, Tiejun Yu |
A Fast Hierarchical Algorithm for 3-D Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 212-217, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
20 | E. Aykut Dengi, Ronald A. Rohrer |
Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 218-223, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
reconstruction, emulation, visibility, functional simulation |
20 | U. Geigenmüller, N. P. van der Meijs |
Cartesian multipole based numerical integration for 3D capacitance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 256-259, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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