Search results for "GLFSR"

Found 7 publication records. Showing 7 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
141	Dhiraj K. Pradhan, Mitrajit Chatterjee	GLFSR-a new test pattern generator for built-in-self-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
61	Mitrajit Chatterjee, Dhiraj K. Pradhan	A novel pattern generator for near-perfect fault-coverage.	VTS	1995	DBLP DOI BibTeX RDF	near-perfect fault-coverage, onchip BIST, GLFSR, logic mapping technique, weighted pattern technique, logic testing, built-in self test, integrated circuit testing, design methodology, combinational circuits, automatic testing, integrated logic circuits, shift registers, combinational logic, digital integrated circuits, pattern generator, single stuck-at fault
42	Dhiraj K. Pradhan, Mitrajit Chatterjee	GLFSR - A New Test Pattern Generator for Built-In Self-Test.	ITC	1994	DBLP DOI BibTeX RDF
25	Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir	A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage.	IOLTS	2005	DBLP DOI BibTeX RDF
25	Mitrajit Chatterjee, Dhiraj K. Pradhan	A BIST Pattern Generator Design for Near-Perfect Fault Coverage.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	core logic, built-in self-test, synthesis, fault coverage, Linear feedback shift registers, test pattern generation, scan, SOC
25	Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly	Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.	VLSI Design	2001	DBLP DOI BibTeX RDF
25	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR

Displaying result #1 - #7 of 7 (100 per page; Change: )