Search results for "Gate-resizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
164	Vijay Sundararajan, Keshab K. Parhi	Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution.	ARVLSI	1999	DBLP DOI BibTeX RDF	Gate-resizing, Buffer-redistribution, near-optimal, library-specific, optimal, low-power
101	Supratik Chakraborty, Rajeev Murgai	Complexity Of Minimum-Delay Gate Resizing.	VLSI Design	2001	DBLP DOI BibTeX RDF
92	Chen-Liang Fang, Wen-Ben Jone	Timing optimization by gate resizing and critical path identification.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
49	Juho Kim, David Hung-Chang Du	Performance optimization by gate sizing and path sensitization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
37	Supratik Chakraborty, Rajeev Murgai	Layout-Driven Timing Optimization by Generalized De Morgan Transform.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
29	R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi	Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
27	Noureddine Chabini, Said Belkouch, Mohamed Najoui	An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs.	ICECOCS	2022	DBLP DOI BibTeX RDF
27	Mohsen Raji, Behnam Ghavami, Hossein Pedram	Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process Variations.	DSD	2015	DBLP DOI BibTeX RDF
27	Rajeev R. Rao, David T. Blaauw, Dennis Sylvester	Soft error reduction in combinational logic using gate resizing and flipflop selection.	ICCAD	2006	DBLP DOI BibTeX RDF
27	Edward Y. C. Cheng, Sartaj Sahni	Gate Resizing to Reduce Power Consumption.	Int. J. Found. Comput. Sci.	2002	DBLP DOI BibTeX RDF
27	Torsten Mahnke, Walter Stechele, Martin Embacher, Wolfgang Hoeld	Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis.	ICECS	2002	DBLP DOI BibTeX RDF
27	Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru	A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design.	DAC	1999	DBLP DOI BibTeX RDF
27	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, D. Severac	A non-iterative gate resizing algorithm for high reduction in power consumption.	Integr.	1997	DBLP DOI BibTeX RDF
27	Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, D. Severac	A gate resizing technique for high reduction in power consumption.	ISLPED	1997	DBLP DOI BibTeX RDF
27	Weitong Chuang, Ibrahim N. Hajj	Delay and area optimization for compact placement by gate resizing and relocation.	ICCAD	1994	DBLP DOI BibTeX RDF
27	Wen-Ben Jone, Chen-Liang Fang	Timing Optimization By Gate Resizing And Critical Path Identification.	DAC	1993	DBLP DOI BibTeX RDF
21	Chanseok Hwang, Chang Woo Kang, Massoud Pedram	Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.	ISQED	2006	DBLP DOI BibTeX RDF
16	Hossein Asadi 0001, Mehdi Baradaran Tahoori	Soft error hardening for logic-level designs.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Justin Hensley, Anselmo Lastra, Montek Singh	A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier.	ASYNC	2005	DBLP DOI BibTeX RDF
16	Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.	VTS	2005	DBLP DOI BibTeX RDF
16	Rajeev Murgai	Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	Justin Hensley, Anselmo Lastra, Montek Singh	An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices.	ICCD	2004	DBLP DOI BibTeX RDF
16	Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin	An Adaptive Interconnect-Length Driven Placer.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
16	Guenter Stenz, Bernhard M. Riess, Bernhard Rohfleisch, Frank M. Johannes	Performance optimization by interacting netlist transformations andplacement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
16	Rajeev Murgai	Performance optimization under rise and fall parameters.	ICCAD	1999	DBLP DOI BibTeX RDF
16	Hsi-Chuan Chen, David Hung-Chang Du, Li-Ren Liu	Critical path selection for performance optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF