Search results for "HLDVT"

Hits ?▲	Authors	Title	Venue	Year	Link
85	Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel	FFT Compiler: from math to efficient hardware HLDVT invited short paper.	HLDVT	2007	DBLP DOI BibTeX RDF
51		2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017, Santa Cruz, CA, USA, October 5-6, 2017	HLDVT	2017	DBLP BibTeX RDF
51	Zhongqi Cheng, Tim Schmidt, Guantao Liu, Rainer Dömer	Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Binod Kumar 0001, Kanad Basu, Masahiro Fujita, Virendra Singh	RTL level trace signal selection and coverage estimation during post-silicon validation.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Zahra Shirmohammadi, Hadi Zamani Sabzi, Seyed Ghassem Miremadi	3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Guy Barash, Eitan Farchi	A randomized algorithm for constructing cross-feature tests from single feature tests.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Sophia Balkovski, Ian G. Harris	Designing cyber-physical systems from natural language descriptions.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Siroos Madani, Kasem Khalil, Bappaditya Dey, Devante Bonton, Magdy A. Bayoumi	Repair techniques for aged TSVs in 3D integrated circuits.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Michele Lora	Validation of HMI applications for industrial smart display.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Tonmoy Roy, Michael Hsiao	Reachability analysis in RTL circuits using k-induction bounded model checking.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi	A novel SAT-based ATPG approach for transition delay faults.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Keerthikumara Devarajegowda, Wolfgang Ecker	On generation of properties from specification.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Daniela De Venuto, Giovanni Mezzina, V. L. Gallo	Design and implementation of FPGA-based muscle conduction velocity tracker in dynamic contractions during the gait.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Pankaj Moharikar, Jayakrishna Guddeti	Automated test generation for post silicon microcontroller validation.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Florenc Demrozi, Riccardo Zucchelli, Graziano Pravadelli	Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Maral Amir, Tony Givargis	HES machine: Harmonic equivalent state machine modeling for cyber-physical systems.	HLDVT	2017	DBLP DOI BibTeX RDF
51	Masahiro Fujita	An approach to approximate computing: Logic transformations for one-minterm changes in specification.	HLDVT	2017	DBLP DOI BibTeX RDF
51		IEEE International High Level Design Validation and Test Workshop, HLDVT 2016, Santa Cruz, CA, USA, October 7-8, 2016	HLDVT	2016	DBLP BibTeX RDF
51	Prab Varma, Miroslav N. Velev	Welcome Message.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Qinhao Wang, Yusuke Kimura, Masahiro Fujita	Automatically adjusting system level designs after RTL/gate-level ECO.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Yusuke Kimura, Masahiro Fujita	Specification by existing design plus use-cases.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Guantao Liu, Tim Schmidt, Rainer Dömer	A segment-aware multi-core scheduler for system C PDES.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Natasa Miskov-Zivanov, Paolo Zuliani, Qinsi Wang, Edmund M. Clarke, James R. Faeder	High-level modeling and verification of cellular signaling.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Md. Ariful Islam, Qinsi Wang, Ramin M. Hasani, Ondrej Balun, Edmund M. Clarke, Radu Grosu, Scott A. Smolka	Probabilistic reachability analysis of the tap withdrawal circuit in caenorhabditis elegans.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Houssam Abbas, Zhihao Jiang, Kuk Jin Jang, Marco Beccani, Jackson Liang, Rahul Mangharam	High-level modeling for computer-aided clinical trials of medical devices.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Sebastian Reiter 0003, Alexander Viehl, Oliver Bringmann 0001, Wolfgang Rosenstiel	Fault injection ecosystem for assisted safety validation of automotive systems.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Jacob A. Abraham	Cross-layer resilience: are high-level techniques always better?	HLDVT	2016	DBLP DOI BibTeX RDF
51	Mejid Kebaili, Jean-Christophe Brignone, Katell Morin-Allory	Clock domain crossing formal verification: a meta-model.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Rosario Distefano, Nickolas Goncharenko, Franco Fummi, Rosalba Giugno, Gary D. Bader, Nicola Bombieri	SyQUAL: a platform for qualitative modelling and simulation of biological systems.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Mohamed O. Kayed, Mohamed Abdelsalam, Rafik Guindi	Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Kasper Søe Luckow, Corina S. Pasareanu	Log2model: inferring behavioral models from log data.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Daniel Yunge, Sangyoung Park, Philipp H. Kindt, Graziano Pravadelli, Samarjit Chakraborty	Dynamic service synthesis and switching for medical IoT and ambient assisted living.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Xian Li 0002, Klaus Schneider 0001	Control-flow guided clause generation for property directed reachability.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Jörg Fickenscher, Oliver Reiche, Jens Schlumberger, Frank Hannig, Jürgen Teich	Modeling, programming and performance analysis of automotive environment map representations on embedded GPUs.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Jason G. Tong, Marc Boule, Zeljko Zilic	Accelerating assertion assessment using GPUs.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Prachi Joshi, Vedahari Narasimhan G., Haibo Zeng 0001, Sandeep K. Shukla, Chung-Wei Lin, Huafeng Yu	Design space exploration for deterministic ethernet-based architecture of automotive systems.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Qinsi Wang, Edmund M. Clarke	Formal modeling of biological systems.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan	Hardware-in-the-loop model-less diagnostic test generation.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Eman El Mandouh, Amr G. Wassal	Estimation of formal verification cost using regression machine learning.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Subarna Sinha, David L. Dill	Deciphering cancer biology using boolean methods.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Johannes Schreiner, Rainer Findenig, Wolfgang Ecker	Design centric modeling of digital hardware.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Daniela De Venuto, Valerio Francesco Annese, Giovanni Mezzina, Michele Ruta, Eugenio Di Sciascio	Brain-computer interface using P300: a gaming approach for neurocognitive impairment diagnosis.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Loïc Besnard, Thierry Gautier, Clément Guy, Paul Le Guernic, Jean-Pierre Talpin, Brian R. Larson, Etienne Borde	Formal semantics of behavior specifications in the architecture analysis and design language standard.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Xiaojun Sun, Priyank Kalla, Florian Enescu	Word-level traversal of finite state machines using algebraic geometry.	HLDVT	2016	DBLP DOI BibTeX RDF
51	Michele Lora, Sara Vinco, Franco Fummi	A unifying flow to ease smart systems integration.	HLDVT	2016	DBLP DOI BibTeX RDF
51		2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, USA, November 9-10, 2012	HLDVT	2012	DBLP BibTeX RDF
51	Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid	Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Mahesh Nanjundappa, Anirudh M. Kaushik, Hiren D. Patel, Sandeep K. Shukla	Accelerating SystemC simulations using GPUs.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler	Behavior Driven Development for circuit design and verification.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Nicola Nicolici	On-chip stimuli generation for post-silicon validation.	HLDVT	2012	DBLP DOI BibTeX RDF
51	An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou	A formal method to improve SystemVerilog functional coverage.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Neil C. Audsley, Ian Gray, Andrea Acquaviva, Ralph Haines	ToucHMore toolchain and system software for energy and variability customisation.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Rainer Findenig, Thomas Leitner, Wolfgang Ecker	Single-source hardware modeling of different abstraction levels with State Charts.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Freek Verbeek, Julien Schmaltz	Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Dogan Ulus, Alper Sen 0001	Using haloes in mixed-signal assertion based verification.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Rolf Drechsler, Ian G. Harris, Robert Wille	Generating formal system models from natural language descriptions.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Bijan Alizadeh, Masahiro Fujita	A functional test generation technique for RTL datapaths.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Diego Braga, Franco Fummi, Graziano Pravadelli, Sara Vinco	The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Romain Lemaire, Sébastien Thuries, Frédéric Heitzmann	A flexible modeling environment for a NoC-based multicore architecture.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Andrea Acquaviva	Energy aware TLM platform simulation via RTL abstraction.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Olfat El-Mahi, Gabriela Nicolescu, Gilles Pesant, Giovanni Beltrame	Embedded system verification through constraint-based scheduling.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Hao Zheng 0001, Andrew Price, Chris J. Myers	Using decision diagrams to compactly represent the state space for explicit model checking.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Ian G. Harris	Automatic generation of Verilog bus transactors from natural language protocol specifications.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir	Emulation in post-silicon validation: It's not just for functionality anymore.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Yu Bai 0003, Jens Brandt 0001, Klaus Schneider 0001	Monitoring distributed reactive systems.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Masahiro Fujita	Post-silicon verification and debugging with control flow traces and patchable hardware.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Weiwei Chen 0001, Che-Wei Chang, Xu Han 0002, Rainer Dömer	Eliminating race conditions in system-level models by using parallel simulation infrastructure.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Simone Bronuzzi, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli	Accurate profiling of oracles for self-checking time-constrained embedded software.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Huy Nguyen, Michael S. Hsiao	Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Kanad Basu, Prabhat Mishra 0001, Priyadarsan Patra	Constrained signal selection for post-silicon validation.	HLDVT	2012	DBLP DOI BibTeX RDF
51	Zeljko Zilic, Sandeep K. Shukla (eds.)	2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011	HLDVT	2011	DBLP BibTeX RDF
51	Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli, Francesco Stefanni, Sara Vinco	UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Jinpeng Lv, Priyank Kalla, Florian Enescu	Verification of composite Galois field multipliers over GF ((2m)n) using computer algebra techniques.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Min Li 0013, Kelson Gent, Michael S. Hsiao	Utilizing GPGPUs for design validation with a modified Ant Colony Optimization.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Hansu Cho, Samar Abdi	Automatic generation of transducer models for multicore system design.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Matin Hashemi, Soheil Ghiasi	Towards scalable utilization of embedded manycores in throughput-sensitive applications.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli	Interactive presentation abstract: Reusing of properties after discretization of hybrid automata.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Alexander W. Rath, Volkan Esen, Wolfgang Ecker	Analog transaction level modeling.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Mike Gemünde, Jens Brandt 0001, Klaus Schneider 0001	Causality analysis of synchronous programs with refined clocks.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Andrea Pellegrini, Valeria Bertacco	Cardio: Adaptive CMPs for reliability through dynamic introspective operation.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Wei Hu, Huy Nguyen, Michael S. Hsiao	Sufficiency-based filtering of invariants for Sequential Equivalence Checking.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Charlie Shucheng Zhu, Georg Weissenbacher, Divjyot Sethi, Sharad Malik	SAT-based techniques for determining backbones for post-silicon fault localisation.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Amir Masoud Gharehbaghi, Masahiro Fujita	Formal verification guided automatic design error diagnosis and correction of complex processors.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Gunar Schirner	Modeling, synthesis, and validation of heterogeneous biomedical embedded systems.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Somnath Banerjee 0003, Tushar Gupta, Saurabh Jain	A scalable hybrid verification system based on HDL slicing.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Tao Xie 0006, Wolfgang Müller 0003, Florian Letombe	IP-XACT based system level mutation testing.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Mehdi Karimibiuki, Kyle Balston, Alan J. Hu, André Ivanov	Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli	Interactive presentation abstract: Assertion-based verification in embedded-software design.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Hans Eveking, Tobias Dornes, Martin Schweikert	Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Bijan Alizadeh, Masahiro Fujita	Modular equivalence verification of polynomial datapaths with multiple word-length operands.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Charalambos Ioannides, Geoff Barrett, Kerstin Eder	Introducing XCS to Coverage Directed test Generation.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Frederic Risacher, Kenneth J. Schultz	Software agnostic approaches to explore pre-silicon system performance.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik	Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams.	HLDVT	2011	DBLP DOI BibTeX RDF
51	Peter Lisherness, Kwang-Ting (Tim) Cheng	Coverage discounting: A generalized approach for testbench qualification.	HLDVT	2011	DBLP DOI BibTeX RDF
51		IEEE International High Level Design Validation and Test Workshop, HLDVT 2010, Anaheim, CA, USA, 10-12 June 2010	HLDVT	2010	DBLP BibTeX RDF
51	Rajiv Bhatia, Eyal Bin, Eitan Marcus, Gil Shurek	An ontology and constraint based approach to cache preloading.	HLDVT	2010	DBLP DOI BibTeX RDF
51	Haiqiong Yao, Hao Zheng 0001, Chris J. Myers	State space reductions for scalable verification of asynchronous designs.	HLDVT	2010	DBLP DOI BibTeX RDF
51	Ashvin Dsouza	Static analysis of deadends in SVA constraints.	HLDVT	2010	DBLP DOI BibTeX RDF
51	Rainer Findenig, Thomas Leitner, Michael Velten, Wolfgang Ecker	Fast and accurate UML State Chart modeling using TLM+ control flow abstraction.	HLDVT	2010	DBLP DOI BibTeX RDF
51	Sumit Ahuja, Wei Zhang, Sandeep K. Shukla	System level simulation guided approach to improve the efficacy of clock-gating.	HLDVT	2010	DBLP DOI BibTeX RDF