Search results for "HiPEAC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
137	Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam	High-Performance Embedded Architecture and Compilation Roadmap.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF	HiPEAC, single core architecture, programming models and tools, simulation and system modelling, real-time systems, compilation, interconnection networks, benchmarking, reconfigurable computing, run-time systems, multi-core architecture, roadmap
111	Christian Bertin, Christophe Guillon, Koen De Bosschere	Compilation and virtualization in the HiPEAC vision.	DAC	2010	DBLP DOI BibTeX RDF	HiPEAC, deferred compilation, embedded virtualization
56	Koen De Bosschere	Upcoming Computing System Challenges - The HiPEAC Vision (Anstehende Herausforderungen der Computer Industrie - Die HiPEAC Vision).	it Inf. Technol.	2008	DBLP DOI BibTeX RDF
45	Marko Bertogna, Federico Terraneo, Federico Reghenzani (eds.)	Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC 2022, June 22, 2022, Budapest, Hungary.	NG-RES@HiPEAC	2022	DBLP BibTeX RDF
45	Daniele Cattaneo 0002, Gabriele Magnani, Stefano Cherubin, Giovanni Agosta	Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time.	NG-RES@HiPEAC	2022	DBLP DOI BibTeX RDF
45	Giorgio C. Buttazzo	Can We Trust AI-Powered Real-Time Embedded Systems? (Invited Paper).	NG-RES@HiPEAC	2022	DBLP DOI BibTeX RDF
45		Front Matter, Table of Contents, Preface, Conference Organization.	NG-RES@HiPEAC	2022	DBLP DOI BibTeX RDF
45	Khalil Esper, Stefan Wildermann, Jürgen Teich	Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study.	NG-RES@HiPEAC	2022	DBLP DOI BibTeX RDF
45	Alberto Leva, Simone Formentin, Silvano Seva	Overlapping-Horizon MPC: A Novel Approach to Computational Constraints in Real-Time Predictive Control.	NG-RES@HiPEAC	2022	DBLP DOI BibTeX RDF
45	Marko Bertogna, Federico Terraneo (eds.)	Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC 2021, January 20, 2021, Budapest, Hungary.	NG-RES@HiPEAC	2021	DBLP BibTeX RDF
45	David García Villaescusa, Mario Aldea Rivas, Michael González Harbour	M2OS-Mc: An RTOS for Many-Core Processors.	NG-RES@HiPEAC	2021	DBLP DOI BibTeX RDF
45	Khalil Esper, Stefan Wildermann, Jürgen Teich	A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper).	NG-RES@HiPEAC	2021	DBLP DOI BibTeX RDF
45		Front Matter, Table of Contents, Preface, Conference Organization.	NG-RES@HiPEAC	2021	DBLP DOI BibTeX RDF
45	Philipp Jungklass, Mladen Berekovic	Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout.	NG-RES@HiPEAC	2021	DBLP DOI BibTeX RDF
45	Miguel Gutiérrez-Gaitán, Luís Almeida 0001, Pedro M. Santos 0002, Patrick Meumeu Yomsi	EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks.	NG-RES@HiPEAC	2021	DBLP DOI BibTeX RDF
45	Silvano Seva, William Fornaciari, Alberto Leva	Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls.	NG-RES@HiPEAC	2021	DBLP DOI BibTeX RDF
45		11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020, Bologna, Italy, January, 2020	PARMA-DITAM@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Marko Bertogna, Federico Terraneo (eds.)	Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC 2020, January 21, 2020, Bologna, Italy.	NG-RES@HiPEAC	2020	DBLP BibTeX RDF
45	José L. Núñez-Yáñez, Kris Nikov, Kerstin Eder, Mohammad Hosseinabady	Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling.	PARMA-DITAM@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Mohammad Hosseinabady, José L. Núñez-Yáñez	Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System.	PARMA-DITAM@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Nicola Fossati, Daniele Cattaneo 0002, Michele Chiari, Stefano Cherubin, Giovanni Agosta	Automated Precision Tuning in Activity Classification Systems: A Case Study.	PARMA-DITAM@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Petr Dobiás, Emmanuel Casseau, Oliver Sinnen	Fault-Tolerant Online Scheduling Algorithms for CubeSats.	PARMA-DITAM@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Vittoriano Muttillo, Paolo Giammatteo, Giuseppe Fiorilli, Luigi Pomante	An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems.	PARMA-DITAM@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Luís Almeida 0001	SDN for Dynamic Reservations on Real-Time Networks (Invited Talk).	NG-RES@HiPEAC	2020	DBLP DOI BibTeX RDF
45		Front Matter, Table of Contents, Preface, Conference Organization.	NG-RES@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Bertrand Simon 0001, Joachim Falk, Nicole Megow, Jürgen Teich	Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice.	NG-RES@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich	Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems.	NG-RES@HiPEAC	2020	DBLP DOI BibTeX RDF
45	José Martins, Adriano Tavares, Marco Solieri, Marko Bertogna, Sandro Pinto 0001	Bao: A Lightweight Static Partitioning Hypervisor for Modern Multi-Core Embedded Systems.	NG-RES@HiPEAC	2020	DBLP DOI BibTeX RDF
45	Silvano Seva, Claudia Esther Lukaschewsky Mauriziano, William Fornaciari, Alberto Leva	A Low Energy FPGA Platform for Real-Time Event-Based Control.	NG-RES@HiPEAC	2020	DBLP DOI BibTeX RDF
45		Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January 23-23, 2018	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Carsten Trinitis, Josef Weidendorfer (eds.)	Proceedings of the 3rd Workshop on Co-Scheduling of HPC Applications, COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018.	COSH@HiPEAC	2018	DBLP BibTeX RDF
45	Vojtech Cima, Stanislav Böhm, Jan Martinovic, Jiri Dvorský, Katerina Janurová, Tom Vander Aa, Thomas J. Ashby, Vladimir I. Chupakhin	HyperLoom: A Platform for Defining and Executing Scientific Pipelines in Distributed Environments.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Hamid Arabnejad, João Bispo, Jorge G. Barbosa, João M. P. Cardoso	AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Michele Zanella, Giuseppe Massari, William Fornaciari	Enabling Run-Time Managed Distributed Mobile Computing.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Robert Khasanov, Andrés Goens, Jerónimo Castrillón	Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Ricardo Nobre, Luís Reis 0001, João Bispo, Tiago Carvalho, João M. P. Cardoso, Stefano Cherubin, Giovanni Agosta	Aspect-Driven Mixed-Precision Tuning Targeting GPUs.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Giovanni Agosta, William Fornaciari, Giuseppe Massari, Anna Pupykina, Federico Reghenzani, Michele Zanella	Managing Heterogeneous Resources in HPC Systems.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Luís Reis 0001, Ricardo Nobre, João M. P. Cardoso	Impact of Vectorization Over 16-bit Data-Types on GPUs.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin J. M. Martin, Benoît Dupont de Dinechin, Jean-François Nezan	Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Lester Kalms, Tim Hebbeler, Diana Göhringer	Automatic OpenCL Code Generation from LLVM-IR using Polyhedral Optimization.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Vittoriano Muttillo, Giacomo Valente, Luigi Pomante	Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Mingze Ma, Rizos Sakellariou	Reducing Code Size in Scheduling Synchronous Dataflow Graphs on Multicore Systems.	PARMA-DITAM@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Carsten Trinitis, Josef Weidendorfer	Foreword by Editors / Workshop Description / TPC List.	COSH@HiPEAC	2018	DBLP BibTeX RDF
45	Andreas de Blanche, Thomas Lundqvist	Node Sharing for Increased Throughput and Shorter Runtimes - an Industrial Co-Scheduling Case Study.	COSH@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Thomas Becker 0008, Dai Yang, Tilman Küstner, Martin Schulz 0001	Co-Scheduling in a Task-Based Programming Model.	COSH@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Martin Schreiber 0001, Tobias Weinzierl	A Case Study for a New Invasive Extension of Intel's Threading Building Blocks.	COSH@HiPEAC	2018	DBLP DOI BibTeX RDF
45	Sören Sonntag, José Manuel García Carrasco, José Luis Abellán Miguel, Daniel Müller-Gritschneder (eds.)	Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45		Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Carsten Trinitis, Josef Weidendorfer (eds.)	Co-Scheduling of HPC Applications [extended versions of all papers from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]	COSH@HiPEAC (extended versions)	2017	DBLP BibTeX RDF
45	Carsten Clauss, Stefan Lankes, Carsten Trinitis, Josef Weidendorfer (eds.)	Proceedings of the Joined Workshops COSH 2017 and VisorHPC 2017, COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017.	COSH/VisorHPC@HiPEAC	2017	DBLP BibTeX RDF
45	Mats Brorsson, Zhonghai Lu, Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi (eds.)	Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24, 2017	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Kari Clark, Phill Watt	Enabling high performance rack-scale optical switching through global synchronisation.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Jeremiah J. Wilke	Bringing minimal routing back to HPC through silicon photonics: a study of "flexfly" architectures with the structural simulation toolkit (SST).	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Benoît Dupont de Dinechin, Amaury Graillat	Network-on-chip service guarantees on the kalray MPPA-256 bostan processor.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Syed Ijlal Shah	Interconnects for next generation SoC designs.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Emmanuel Ofori-Attah, Michael Opoku Agyeman	A survey of low power NoC design techniques.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Muhammad Obaidullah, Gul N. Khan	Optimal application mapping to 2D-mesh NoCs by using a tabu-based particle swarm methodology.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Fernando Pereñíguez-Garcia, José L. Abellán	Secure communications in wireless network-on-chips.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Monobrata Debnath, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Wei-Ming Lin, Junghee Lee	Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Marco Balboni, Davide Bertozzi	Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Jean-Pierre Panziera	BXI: designing a network for eXascale.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	François Abel, Andreas Doering	Microserver + micro-switch = micro-datacenter.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Nikos Pleros, Nikos Terzenidis, Theoni Alexoudi, K. Vyrsokinos, George T. Kanellos, Dimitris Syrivelis	Software-defined board- and chip-level optical interconnects for multi-socket communication and disaggregated computing.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Yong Hu, Daniel Müller-Gritschneder, Ulf Schlichtmann	Model-based framework for networks-on-chip design space exploration.	AISTECS@HiPEAC	2017	DBLP DOI BibTeX RDF
45	María H. Auras-Rodríguez, Anthony Zimmermann, Gerd Ascheid, Rainer Leupers	Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition.	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Nicholas J. Fraser, Yaman Umuroglu, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers	Scaling Binarized Neural Networks on Reconfigurable Logic.	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Michail Doukas, Sotirios Xydis, Dimitrios Soudris	Dataflow Acceleration of scikit-learn Gaussian Process Regression.	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Yu Yang, Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis 0001	MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs.	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Lu Li 0001, Christoph W. Kessler	VectorPU: A Generic and Efficient Data-container and Component Model for Transparent Data Transfer on GPU-based Heterogeneous Systems.	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	David Pereira, Aleksandar Ilic, Leonel Sousa	On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory.	PARMA-DITAM@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Andreas de Blanche, Thomas Lundqvist	Disallowing Same-program Co-schedules to Improve Efficiency in Quad-core Servers.	COSH/VisorHPC@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Ioannis A. Papadakis, Konstantinos Nikas, Vasileios Karakostas, Georgios I. Goumas, Nectarios Koziris	Improving QoS and Utilisation in modern multi-core servers with Dynamic Cache Partitioning.	COSH/VisorHPC@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Shiqing Fan, Fang Chen, Holm Rauchfuss, Nadav Har'El, Uwe Schilling, Nico Struckmann	Towards a Lightweight RDMA Para-Virtualization for HPC.	COSH/VisorHPC@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Simon Pickartz, Jens Breitbart, Stefan Lankes	Co-scheduling on Upcoming Many-Core Architectures.	COSH/VisorHPC@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Tilman Küstner, Carsten Trinitis, Josef Weidendorfer, Andreas Blaszczyk, Patrik Kaufmann, Marcus Johansson	On the Applicability of Virtualization in an Industrial HPC Environment.	COSH/VisorHPC@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Hermann Seuschek, Fabrizio De Santis, Oscar M. Guillen	Side-channel leakage aware instruction scheduling.	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Karim M. Abdellatif, Damien Couroussé, Olivier Potin, Philippe Jaillon	Filtering-based CPA: a successful side-channel attack against desynchronization countermeasures.	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Sha Tao, Elena Dubrova	Reliable low-overhead arbiter-based physical unclonable functions for resource-constrained IoT devices.	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Florian Wilde	Large scale characterization of SRAM on infineon XMC microcontrollers as PUF.	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Frank K. Gürkaynak, Robert Schilling, Michael Muehlberghuber, Francesco Conti 0001, Stefan Mangard, Luca Benini	Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS.	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45	Miraje Gentilal, Paulo Martins 0002, Leonel Sousa	TrustZone-backed bitcoin wallet.	CS2@HiPEAC	2017	DBLP DOI BibTeX RDF
45		Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech Republic, January 18, 2016	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Sergey Tverdyshev (eds.)	International Workshop on MILS: Architecture and Assurance for Secure Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016.	MILS@HiPEAC	2016	DBLP BibTeX RDF
45	Sören Sonntag, Sandro Bartolini, Giorgos Dimitrakopoulos, José M. García 0001 (eds.)	Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016	AISTECS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Carsten Trinitis, Josef Weidendorfer (eds.)	Proceedings of the 1st COSH Workshop on Co-Scheduling of HPC Applications, COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016.	COSH@HiPEAC	2016	DBLP BibTeX RDF
45	Martin Palkovic, Giovanni Agosta, Alessandro Barenghi, Israel Koren, Gerardo Pelosi (eds.)	Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, CS2@HiPEAC, Prague, Czech Republic, January 20, 2016	CS2@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Gereon Onnebrink, Stefan Schürmans, Florian Walbroel, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, YwhPyng Harn	Black box power estimation for digital signal processors using virtual platforms.	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Khalid Latif 0003, Manuel Selva, Charles Effiong, Roman Ursu, Abdoulaye Gamatié, Gilles Sassatelli, Leonardo Bonet Zordan, Luciano Ost, Piotr Dziurzanski, Leandro Soares Indrusiak	Design space exploration for complex automotive applications: an engine control system case study.	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Guillaume Sarrazin, Nicolas Brunie, Frédéric Pétrot	Virtual prototyping of floating point units.	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Patrick Siegl, Rainer Buchty, Mladen Berekovic	Towards bridging the gap between academic and industrial heterogeneous system architecture design space exploration.	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Martin Flasskamp, Gregor Sievers, Johannes Ax, Christian Klarhorst, Thorsten Jungeblut, Wayne Kelly, Michael Thies, Mario Porrmann	Performance estimation of streaming applications for hierarchical MPSoCs.	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Naveed Ul Mustafa, Ozcan Ozturk 0001, Smaïl Niar	Adaptive routing framework for network on chip architectures.	RAPIDO@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Sergey Tverdyshev	EURO-MILS: Building and certifying modular secure systems.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Ruud Koolen, Julien Schmaltz	Modeling Information Routing with Noninterference.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Paul J. Parkinson	Applying MILS to multicore avionics systems.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Igor Furgel, Viola Saftig, Tobias Wagner, Kevin Müller, Reinhard Schwarz, Axel Söding-Freiherr von Blomberg	Non-Interfering Composed Evaluation.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Hans-Jürgen Herpel, M. Kerep, G. Montano, Knut Eckstein, M. Schön, A. Krutak	MILS Compliant Software Architecture for Satellites.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Tobias Rauter, Andrea Höller, Nermin Kajtazovic, Christian Kreiner	Asset-Centric Security Risk Assessment of Software Components.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Julien Delange, Min-Young Nam, Peter H. Feiler, Will Klieber	An Architecture-Centric Process for MILS Development.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF
45	Tomasz Maciazek, Hanne Riis Nielson, Flemming Nielson	Content-Dependent Security Policies in Avionics.	MILS@HiPEAC	2016	DBLP DOI BibTeX RDF