Search results for "INL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
156	Yi Lu Murphey, ZhiHang Chen, Lee A. Feldkamp	An incremental neural learning framework and its application to vehicle diagnostics.	Appl. Intell.	2008	DBLP DOI BibTeX RDF	Vehicle diagnostics, Neural networks, Incremental learning
138	Vincent Kerzerho, Serge Bernard, Philippe Cauvet, Jean-Marie Janik	A First Step for an INL Spectral-Based BIST: The Memory Optimization.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	integral non-linearity, polynomial fitting, Fourier series expansion, fast Fourier transform, analog-to-digital converter testing
138	Marko Kosunen, Jouko Vankka, Ilari Teikari, Kari Halonen	DNL and INL yield models for a current-steering D/A converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
67	Gholamreza Nikandish, Behnam Sedighi, Mehrdad Sharif Bakhtiar	INL Prediction Method in Pipeline ADCs.	APCCAS	2006	DBLP DOI BibTeX RDF
60	Mehdi Ehsanian, Bozena Kaminska, Karim Arabi	A new digital test approach for analog-to-digital converter testing.	VTS	1996	DBLP DOI BibTeX RDF	digital test approach, analog/digital converter testing, BIST circuitry, offset error, gain error, DNL, INL, area overhead reduction, medium resolution ADC, high resolution pipelined ADC, A/D converter testing, differential nonlinearity, integral nonlinearity, 1.5 micron, VLSI, built-in self test, built-in self-test, integrated circuit testing, CMOS integrated circuits, CMOS technology, analogue-digital conversion
53	Jingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li 0004, Zhihua Wang 0001	A Pipelined A/D Conversion Technique with Low INL and DNL.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Guo Yu, Peng Li 0001, Wei Dong 0002	Achieving Low-Cost Linearity Test and Diagnosis of Sigma Delta ADCs via Frequency-Domain Nonlinear Analysis and Macromodeling.	ISQED	2007	DBLP DOI BibTeX RDF
39	Zhongjun Yu, Degang Chen 0001, Randall L. Geiger	1-D and 2-D switching strategies achieving near optimal INL for thermometer-coded current steering DACs.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
32	Alok Barua, Md. Tausiff	A Code Width Built-In-Self Test Circuit for 8-bit Pipelined ADC.	ICSEng	2011	DBLP DOI BibTeX RDF	Code width, DNL, INL, Missing code fault, BIST, fault coverage
31	Esa Korhonen, Juha Kostamovaara	An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing.	ETS	2008	DBLP DOI BibTeX RDF	histogram test, integral non-linearity (INL), stimulus identification, built-in self-test (BIST), A/D converter (ADC)
28	Shalabh Goyal, Abhijit Chatterjee	Linearity Testing of A/D Converters Using Selective Code Measurement.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Testing, Non-linearity, Manufacturing test, Analog-digital conversion
28	Xinsong Zhang, Simon S. Ang, Chandra Carter	Comparison of NIST and Wavelet Transform Test Point Selection Methods For a Programmable Gain Amplifier.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Test point selection, NIST method, Programmable gain amplifier, Integral nonlinearity, Wavelet transform
28	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
28	M. Khalilzadeh Agdam, Abdolreza Nabavi	A Low-Power High-Speed 4-Bit ADC for DS-UWB Communications.	ISVLSI	2007	DBLP DOI BibTeX RDF
28	Masoud Babaie, Hamid Movahedian, Mehrdad Sharif Bakhtiar	A Novel Method for Systematic Error Prediction of CMOS Folding and Interpolating ADC.	APCCAS	2006	DBLP DOI BibTeX RDF
28	Yongsheng Wang, Jinxiang Wang 0001, Fengchang Lai, Yizheng Ye	Optimal Schemes for ADC BIST Based on Histogram.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
28	João Goes, Nuno Paulino 0002, Guiomar Evans	On-chip built-in self-test of video-rate ADCs using Gaussian noise.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
28	Sunil Rafeeque, Vinita Vasudevan	A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	digital to analog converters, nonlinearity test, analog testing, mixed-signal BIST
28	Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang	An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
28	Jeng-Horng Tsai, Ming-Jun Hsiao, Tsin-Yuan Chang	An Embedded Built-in-Self-Test Approach for Digital-to-Analog Converters.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
28	Yuan-Tzu Ting, Li Wei Chao, Wei Chung Chao	A Practical Implementation Of Dynamic Testing Of An Ad Converter.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	AD converter, effective bits, differential nonlinearity, integral nonlinearity, mixed frequency estimation algorithm, weighted least square method, spectral average method, frequency domain estimation, logical analyzer, instrument controller, high speed data acquisition device, GPIB, Datel ADC-HS12B, programmable signal generator, algorithm, software, automatic testing, histogram, PC, signal to noise ratio, analogue-digital conversion, dynamic testing
25	Yang Chen, Binyu Cai, Changhuan Chen, Weiliang Peng, Quan Sun, Xiaofei Wang, Hong Zhang 0009	A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
25	Mikhail M. Pilipko, Mikhail S. Yenuchenko	Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
25	Xiaohui Guo, Xu Yan, Shimin Ma, Xinyi Zhang, Ziaho Yan, Anqi Zhang, Kai Xu, Liangping Hua, Yan Du, Hao Wang, Yuxin Shu, Weiqiang Hong, Yunong Zhao, Yaohua Xu	Wavelet decomposition and reconstruction-based INL method for testing high-precision ADC.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
25	Yang Chen, Binyu Cai, Changhuan Chen, Quan Sun, Xiaofei Wang, Hong Zhang	A 1.2-mA Fast-Charge Input Buffer with CLS for 4-MS/s SC Oversampling ADC Achieving +1-2.5-ppm/FSR INL.	ICTA	2023	DBLP DOI BibTeX RDF
25	Yumeng Yang, Wei Deng 0001, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang 0001, Baoyong Chi	A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1st/2nd-Order DTC INL Calibration.	ISSCC	2023	DBLP DOI BibTeX RDF
25	Seyed Mehrdad Babamir, Behzad Razavi	Relation Between INL and ACPR of RF DACs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
25	Yifeng Han, Xi Chen, Songjie Zhang, Donglian Qi	iNL: Implicit non-local network.	Neurocomputing	2022	DBLP DOI BibTeX RDF
25	Alessandro Catania, Andrea Ria, Giuseppe Manfredini, Michele Dei, Massimo Piotto, Paolo Bruschi	A 150 mV, Sub-1 nW, 0.75%-Full-Scale INL Delta-Sigma ADC for Power-Autonomous Sensor Nodes.	ESSCIRC	2022	DBLP DOI BibTeX RDF
25	Jesper Steensgaard, Richard Reay, Raymond Perry, Dave Thomas, Geoffrey Tu, George Reitsma	A 24b 2MS/s SAR ADC with 0.03ppm INL and 106.3dB DR in 180nm CMOS.	ISSCC	2022	DBLP DOI BibTeX RDF
25	Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini	A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
25	Masayoshi Todorokihara	A 9 ps DNL/INL/RMS FPGA-Based Sigma Accumulation TDC with Unlimited Dynamic Range for Time-Based Analog Front End Applications.	IEEE SENSORS	2021	DBLP DOI BibTeX RDF
25	Peng Chen 0022, Feifei Zhang, Suoping Hu, Robert Bogdan Staszewski	A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range.	VLSI Circuits	2021	DBLP DOI BibTeX RDF
25	Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini	A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL.	CoRR	2020	DBLP BibTeX RDF
25	Mikhail S. Yenuchenko, Mikhail M. Pilipko	Reshuffled Diagonal Rotated Walk Switching Scheme for DAC INL Reduction.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
25	Antonio J. Ginés, Gildas Léger, Eduardo J. Peralías	Non-Linear Calibration of Pipeline ADCs using a Histogram-Based Estimation of the Redundant INL.	NEWCAS	2020	DBLP DOI BibTeX RDF
25	Su-Hao Wu, Yun-Shiang Shu, Albert Yen-Chih Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh	9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s.	ISSCC	2020	DBLP DOI BibTeX RDF
25	Marcel Runge, Dario Schmock, Enne Wittenhagen, Friedel Gerfers	A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX.	ISCAS	2020	DBLP DOI BibTeX RDF
25	Jaehoon Jun, Soungchul Park, Junho Kang, Suhwan Kim	A 22-bit Read-Out IC With 7-ppm INL and Sub-100-µHz 1/ f Corner for DC Measurement Systems.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
25	Haoyun Jiang, Zherui Zhang, Zhengkun Shen, Xiucheng Hao, Zexue Liu, Heyi Li, Yi Tan, Qiang Zhou, Junhua Liu, Huailin Liao	A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator.	ISCAS	2019	DBLP DOI BibTeX RDF
25	Hua Fan 0001, Chen Wang, Hailiang Xiong, Quanyuan Feng, Dagang Li, Kelin Zhang, Xiaopeng Diao, Lishuang Lin, Hadi Heidari	A Bit Cycling Method for Improving the DNL/INL in Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).	NGCAS	2018	DBLP DOI BibTeX RDF
25	Ahmed Elmallah, Mostafa Gamal Ahmed, Ahmed Elkholy, Woo-Seok Choi, Pavan Kumar Hanumolu	A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS.	CICC	2018	DBLP DOI BibTeX RDF
25	Chung-Lun Hsu, Drew A. Hall	A current-measurement front-end with 160dB dynamic range and 7ppm INL.	ISSCC	2018	DBLP DOI BibTeX RDF
25	Hongxing Li, Mark Maddox, Michael C. W. Coln, William Buckley, Derek Hummerston, Naveed Naeem	A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3ppm INL.	ISSCC	2018	DBLP DOI BibTeX RDF
25	Haoyun Jiang, Zexue Liu, Xiucheng Hao, Zherui Zhang, Zhengkun Shen, Heyi Li, Junhua Liu, Huailin Liao	A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator.	ISCAS	2018	DBLP DOI BibTeX RDF
25	Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda	Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
25	Amaravati Anvesha, Shaojie Xu, Justin Romberg, Arijit Raychowdhury	A 65nm compressive-sensing time-based ADC with embedded classification and INL-aware training for arrhythmia detection.	BioCAS	2017	DBLP DOI BibTeX RDF
25	Hechen Wang, Fa Foster Dai, Hua Wang 0006	A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization.	CICC	2017	DBLP DOI BibTeX RDF
25	Sebastian Sievert, Ofir Degani, Assaf Ben Bassat, Rotem Banin, Ashoke Ravi, Wolfgang Thomann, Bernd-Ulrich Klepser, Zdravko Boos, Doris Schmitt-Landsiedel	A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
25	Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang	Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs.	IEEE Trans. Instrum. Meas.	2016	DBLP DOI BibTeX RDF
25	Sebastian Sievert, Ofir B. Degani, Assaf Ben Bassat, Rotem Banin, Ashoke Ravi, Bernd-Ulrich Klepser, Zdravko Boos, Doris Schmitt-Landsiedel	2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS.	ISSCC	2016	DBLP DOI BibTeX RDF
25	Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura	19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC.	ISSCC	2016	DBLP DOI BibTeX RDF
25	Shankar Thirunakkarasu, Bertan Bakkaloglu	Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
25	Xu Zhang, Chongli Cai, Hao Meng, Siva Sudani, Randall L. Geiger, Degang Chen 0001	A calibration technique for SAR analog-to-digital converter based on INL testing with quantization bits and redundant bit.	ISCAS	2015	DBLP DOI BibTeX RDF
25	Eduardo J. Peralías, Antonio Jose Ginés, Adoración Rueda	INL systematic reduced-test technique for Pipeline ADCs.	ETS	2014	DBLP DOI BibTeX RDF
25	Roddy C. McLachlan, Alan Gillespie, Michael C. W. Coln, Douglas Chisholm, Denise T. Lee	A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
25	Youngcheol Chae, Kamran Souri, Kofi A. A. Makinwa	A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
25	Valery L. Mironov, Konstantin V. Muzalevskiy, Igor V. Savin	Retrieving Temperature Gradient in Frozen Active Layer of Arctic Tundra Soils From Radiothermal Observations inL-Band - Theoretical Modeling.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2013	DBLP DOI BibTeX RDF
25	Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell	A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
25	Henry Park, Chih-Kong Ken Yang	An INL Yield Model of the Digital-to-Analog Converter.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
25	James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada	A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset.	CICC	2013	DBLP DOI BibTeX RDF
25	Daniele Raiteri, Pieter van Lieshout, Arthur H. M. van Roermund, Eugenio Cantatore	An organic VCO-based ADC for quasi-static signals achieving 1LSB INL at 6b resolution.	ISSCC	2013	DBLP DOI BibTeX RDF
25	Youngcheol Chae, Kamran Souri, Kofi A. A. Makinwa	A 6.3µW 20b incremental zoom-ADC with 6ppm INL and 1µV offset.	ISSCC	2013	DBLP DOI BibTeX RDF
25	Petr Suchánek, Vladimír Haasz, David Slepicka	ADC non-linearity correction based on INL(n) approximation - Experimental verification.	IDAACS	2013	DBLP DOI BibTeX RDF
25	Gaurav Singh, Rong Wu, Youngcheol Chae, Kofi A. A. Makinwa	A 20bit continuous-time ΣΔ modulator with a Gm-C integrator, 120dB CMRR and 15 ppm INL.	ESSCIRC	2012	DBLP DOI BibTeX RDF
25	Esa Korhonen, Juha Kostamovaara	Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs.	ETS	2011	DBLP DOI BibTeX RDF	didital-analog conversion, algorithms, testing, histograms, linearity, analog-digital conversion
25	Esa Korhonen, Carsten Wegener, Juha Kostamovaara	Combining the Standard Histogram Method and a Stimulus Identification Algorithm for A/D Converter INL Testing With a Low-Quality Sine Wave Stimulus.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
25	Jingbo Duan, Le Jin, Degang Chen 0001	INL based dynamic performance estimation for ADC BIST.	ISCAS	2010	DBLP DOI BibTeX RDF
25	Jingbo Duan, Le Jin, Degang Chen 0001	A new method for estimating spectral performance of ADC from INL.	ITC	2010	DBLP DOI BibTeX RDF
25	Seyed Yahya Mortazavi, Abdolreza Nabavi	A New folding & interpolating ADC structure with reduced DNL/INL.	IEICE Electron. Express	2009	DBLP DOI BibTeX RDF
25	Esa Korhonen, Juha Kostamovaara	A loopback-based INL test method for D/A and A/D converters employing a stimulus identification technique.	DATE	2009	DBLP DOI BibTeX RDF
25	Jean-Marie Janik, Vincent Fresnaud	A spectral approach to estimate the INL of A/D converter.	Comput. Stand. Interfaces	2007	DBLP DOI BibTeX RDF
25	Georgi I. Radulov, Markus Heydenreich, Remco van der Hofstad, Johannes A. Hegt, Arthur H. M. van Roermund	Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch.	IEEE Trans. Circuits Syst. II Express Briefs	2007	DBLP DOI BibTeX RDF
25	Fabrizio Stefani, David Macii, Antonio Moschitta, Paolo Carbone, Dario Petri	Simple and time-effective procedure for ADC INL estimation.	IEEE Trans. Instrum. Meas.	2006	DBLP DOI BibTeX RDF
25	Vincent Quiquempoix, Philippe Deval, Alexandre Barreto, Gabriele Bellini, Jerry Collings, János Márkus, José B. Silva, Gabor C. Temes	A low-power 22-bit incremental ADC with 4 ppm INL, 2 ppm gain error and 2 μV DC offset.	ESSCIRC	2005	DBLP DOI BibTeX RDF
25	Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	INL and DNL estimation based on noise for ADC test.	IEEE Trans. Instrum. Meas.	2004	DBLP DOI BibTeX RDF
25	Filippo Attivissimo, Nicola Giaquinto, Izzet Kale	INL reconstruction of A/D converters via parametric spectral estimation.	IEEE Trans. Instrum. Meas.	2004	DBLP DOI BibTeX RDF
25	Carsten Wegener, Michael Peter Kennedy	Testing ADCs for static and dynamic INL - killing two birds with one stone.	Comput. Stand. Interfaces	2004	DBLP DOI BibTeX RDF
25	Tao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen	A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL.	ESSCIRC	2004	DBLP DOI BibTeX RDF
25	Shinichi Hisano, Scott E. Sapp	A 16-bit, 20MSPS CMOS pipeline ADC with direct INL detection algorithm.	CICC	2003	DBLP DOI BibTeX RDF
25	Yonghua Cong, Randall L. Geiger	Formulation of INL and DNL yield estimation in current-steering D/A converters.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
25	Sasikumar Cherubal, Abhijit Chatterjee	Optimal INL/DNL testing of A/D converters using a linear model.	ITC	2000	DBLP DOI BibTeX RDF
14	Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A low power, variable resolution two-step flash ADC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	two-step flash ADC, variable resolution, low power
14	Hee-Cheol Choi, Young-Ju Kim, Se-Won Lee, Jae-Yeol Han, Oh-Bong Kwon, Younglok Kim, Seung-Hoon Lee	A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free dual-channel Nyquist ADC based on mid-code calibration.	ISCAS	2008	DBLP DOI BibTeX RDF
14	He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins	A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Santanu Sarkar 0002, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee	An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.	ISCAS	2008	DBLP DOI BibTeX RDF
14	B. Robert Gregoire, Un-Ku Moon	Reducing the effects of component mismatch by using relative size information.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Chanyang Joo, Soojae Kim, Kwangsub Yoon	A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	binary decoder, pseudo-segmentation, swing reduced driver, low power, DAC
14	David J. Bruemmer, Curtis W. Nielsen, David I. Gertman	How training and experience affect the benefits of autonomy in a dirty-bomb experiment.	HRI	2008	DBLP DOI BibTeX RDF	expert user, seamless autonomy, human-robot interaction, map-building
14	Shangquan Liang, Minglun Gao, Yong-Sheng Yin, Honghui Deng	A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications.	DELTA	2008	DBLP DOI BibTeX RDF	segmented current-steering, pseudorandom switching sequence, current switch driving circuit, unit current-cell
14	Curtis W. Nielsen, David J. Bruemmer	Hiding the System from the User: Moving from Complex Mental Models to Elegant Metaphors.	RO-MAN	2007	DBLP DOI BibTeX RDF
14	Erdem Serkan Erdogan, Sule Ozev	An ADC-BiST scheme using sequential code analysis.	DATE	2007	DBLP DOI BibTeX RDF
14	Hugo Daniel Hernández, Wilhelmus A. M. Van Noije, Elkim Roa, João Navarro Jr.	A small area 8bits 50MHz CMOS DAC for bluetooth transmitter.	SBCCI	2007	DBLP DOI BibTeX RDF	current-steering segmented, low area, bluetooth
14	Karim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud	A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee	A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio	A 12-bit Current-Steering DAC with Calibration by Combination Selection.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire	On-Line Histogram Equalization for Flash ADC.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Hong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai	A New Cycle-Time-to-Digital Converter With Two Level Conversion Scheme.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli	A Power Optimized Base-Band Circuitry for the Low-IF Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
14	Wen-Shen Chou, Shu-Chieh Yang, Fu-Lung Hsueh, Heng-Chang Huang, Chih-Ji Hsiao	A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process.	ISCAS	2007	DBLP DOI BibTeX RDF