Search results for "Iterative-logic-arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
55	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
53	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
53	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
53	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
43	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	General BIST-Amenable Method of Test Generation for Iterative Logic Arrays.	VTS	2000	DBLP DOI BibTeX RDF	fixed-coverage fixed-size test set, test generation, BIST, iterative logic arrays
43	Shih-Yuang Su, Cheng-Wen Wu	Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
43	Abhijit Chatterjee, Jacob A. Abraham	Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	cell states model, two-dimensional iterative logic arrays, ILA cell truth table, cell interconnection structure, bilateral direction, signal flow, horizontal axis, logic testing, graphs, test generation, integrated circuit testing, automatic testing, logic arrays, test set, N-cube
43	Cheng-Wen Wu, Peter R. Cappello	Easily Testable Iterative Logic Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	easily testable iterative logic arrays, octagonally connected arrays, combinational arrays, inhomogeneous arrays, bilateral arrays, test complexity, pipelined arrays, logic testing, systolic arrays, upper bound, matrix multiplication, cellular arrays, combinatorial circuits, multidimensional arrays
43	Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson	LILA: layout generation for iterative logic arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
38	Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu	C-testable design techniques for iterative logic arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
29	Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang	Cell delay fault testing for iterative logic arrays.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	cell delay fault, path delay fault, C-testable, iterative logic array, pseudoexhaustive testing
26	Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	Testing and testable designs for one-time programmable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
26	Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi	Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays.	FPGA	1995	DBLP DOI BibTeX RDF	constant testability, FPGA, testing, manufacturing
25	Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.	DFT	1998	DBLP DOI BibTeX RDF	robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
25	Martine D. F. Schlag, F. Joel Ferguson	Detection of Multiple Faults in Two-Dimensional ILAs.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	testing, functional testing, multipliers, multiple faults, Iterative logic arrays
25	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
25	Wu-Tung Cheng, Janak H. Patel	A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	minimum test set, testing, Adders, iterative logic arrays, multiple fault detection
25	Thirumalai Sridhar, John P. Hayes	A Functional Approach to Testing Bit-Sliced Microprocessors.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Bit-sliced processors, test generation, fault modeling, microprocessors, testability, iterative logic arrays
25	Thirumalai Sridhar, John P. Hayes	Design of Easily Testable Bit-Sliced Systems.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Bit-sliced systems, test generation, design for testability, fault modeling, self-testing, iterative logic arrays
25	Shyue-Kung Lu, Chien-Hung Yeh	Enhancing Delay Fault Testability for Iterative Logic Array.	PRDC	2002	DBLP DOI BibTeX RDF
19	Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama	Built-in self test for C-testable ILA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
18	Avik Chakraborty	Testability of AND-EXOR Based Iterative Logic Arrays	CoRR	2008	DBLP BibTeX RDF
18	Nabil M. Abdulrazzaq, Sandeep K. Gupta 0001	Test generation for path-delay faults in one-dimensional iterative logic arrays.	ITC	2000	DBLP DOI BibTeX RDF
18	Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll	A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays.	ASAP	1997	DBLP DOI BibTeX RDF
18	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing CMOS combinational iterative logic arrays for realistic faults.	Integr.	1996	DBLP DOI BibTeX RDF
18	Bernd Becker 0001, Ralf Hahn, Joachim Hartmann, Uwe Sparmann	On the testability of iterative logic arrays.	Integr.	1995	DBLP DOI BibTeX RDF
18	Arthur D. Friedman	A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF
18	Bernd Becker 0001, Joachim Hartmann	Some Remarks on the Test Complexity of Iterative Logic Arrays.	MFCS	1992	DBLP DOI BibTeX RDF
18	Michael Nicolaidis	Improving the theory of truth table verification of iterative logic arrays.	VTS	1992	DBLP DOI BibTeX RDF
18	Cheng-Wen Wu	Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays.	J. Inf. Sci. Eng.	1990	DBLP BibTeX RDF
18	Tsu-Wei Ku, Mani Soma	Minimal overhead modification of iterative logic arrays for C-testability.	ITC	1990	DBLP DOI BibTeX RDF
18	Abhijit Chatterjee, Jacob A. Abraham	NCUBE: an automatic test generation program for iterative logic arrays.	ICCAD	1988	DBLP DOI BibTeX RDF
18	Wu-Tung Cheng, Janak H. Patel	Multiple-Fault Detection in Iterative Logic Arrays.	ITC	1985	DBLP BibTeX RDF
18	Wu-Tung Cheng	Testing and Error Detection in Iterative Logic Arrays		1985	RDF
18	R. Parthasarathy, Sudhakar M. Reddy	A Testable Design of Iterative Logic Arrays.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF
18	Premachandran R. Menon, Arthur D. Friedman	Fault Detection in Iterative Logic Arrays.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
15	Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin	Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.	VTS	1999	DBLP DOI BibTeX RDF
15	Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar	Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	mutual checking, multiple signature testing, self loops, built-in self test, aliasing
10	Chanyutt Arjhan, Raghvendra G. Deshmukh	A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
10	Abhijit Chatterjee, Jacob A. Abraham	Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
10	Y. You, John P. Hayes	Implementation of VLSI self-testing by regularization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF