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Searching for phrase Iterative-logic-arrays (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1971-1992 (16) 1994-1998 (16) 1999-2008 (9)
Publication types (Num. hits)
article(24) inproceedings(16) phdthesis(1)
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The graphs summarize 93 occurrences of 51 keywords

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Found 41 publication records. Showing 41 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
55Avik Chakraborty Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
53Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
53Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis Robust Sequential Fault Testing of Iterative Logic Arrays. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
53Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis Testing combinational iterative logic arrays for realistic faults. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
43Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF fixed-coverage fixed-size test set, test generation, BIST, iterative logic arrays
43Shih-Yuang Su, Cheng-Wen Wu Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
43Abhijit Chatterjee, Jacob A. Abraham Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1991 DBLP  DOI  BibTeX  RDF cell states model, two-dimensional iterative logic arrays, ILA cell truth table, cell interconnection structure, bilateral direction, signal flow, horizontal axis, logic testing, graphs, test generation, integrated circuit testing, automatic testing, logic arrays, test set, N-cube
43Cheng-Wen Wu, Peter R. Cappello Easily Testable Iterative Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF easily testable iterative logic arrays, octagonally connected arrays, combinational arrays, inhomogeneous arrays, bilateral arrays, test complexity, pipelined arrays, logic testing, systolic arrays, upper bound, matrix multiplication, cellular arrays, combinatorial circuits, multidimensional arrays
43Qinghong Wu, C. Y. Roger Chen, Bradley S. Carlson LILA: layout generation for iterative logic arrays. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
38Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu C-testable design techniques for iterative logic arrays. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
29Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang Cell delay fault testing for iterative logic arrays. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF cell delay fault, path delay fault, C-testable, iterative logic array, pseudoexhaustive testing
26Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi Testing and testable designs for one-time programmable FPGAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
26Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF constant testability, FPGA, testing, manufacturing
25Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
25Martine D. F. Schlag, F. Joel Ferguson Detection of Multiple Faults in Two-Dimensional ILAs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1996 DBLP  DOI  BibTeX  RDF testing, functional testing, multipliers, multiple faults, Iterative logic arrays
25Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis C-Testable modified-Booth multipliers. Search on Bibsonomy J. Electron. Test. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
25Wu-Tung Cheng, Janak H. Patel A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1987 DBLP  DOI  BibTeX  RDF minimum test set, testing, Adders, iterative logic arrays, multiple fault detection
25Thirumalai Sridhar, John P. Hayes A Functional Approach to Testing Bit-Sliced Microprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1981 DBLP  DOI  BibTeX  RDF Bit-sliced processors, test generation, fault modeling, microprocessors, testability, iterative logic arrays
25Thirumalai Sridhar, John P. Hayes Design of Easily Testable Bit-Sliced Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1981 DBLP  DOI  BibTeX  RDF Bit-sliced systems, test generation, design for testability, fault modeling, self-testing, iterative logic arrays
25Shyue-Kung Lu, Chien-Hung Yeh Enhancing Delay Fault Testability for Iterative Logic Array. Search on Bibsonomy PRDC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
19Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama Built-in self test for C-testable ILA's. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
18Avik Chakraborty Testability of AND-EXOR Based Iterative Logic Arrays Search on Bibsonomy CoRR The full citation details ... 2008 DBLP  BibTeX  RDF
18Nabil M. Abdulrazzaq, Sandeep K. Gupta 0001 Test generation for path-delay faults in one-dimensional iterative logic arrays. Search on Bibsonomy ITC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
18Michael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays. Search on Bibsonomy ASAP The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
18Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis Testing CMOS combinational iterative logic arrays for realistic faults. Search on Bibsonomy Integr. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
18Bernd Becker 0001, Ralf Hahn, Joachim Hartmann, Uwe Sparmann On the testability of iterative logic arrays. Search on Bibsonomy Integr. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
18Arthur D. Friedman A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
18Bernd Becker 0001, Joachim Hartmann Some Remarks on the Test Complexity of Iterative Logic Arrays. Search on Bibsonomy MFCS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
18Michael Nicolaidis Improving the theory of truth table verification of iterative logic arrays. Search on Bibsonomy VTS The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
18Cheng-Wen Wu Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays. Search on Bibsonomy J. Inf. Sci. Eng. The full citation details ... 1990 DBLP  BibTeX  RDF
18Tsu-Wei Ku, Mani Soma Minimal overhead modification of iterative logic arrays for C-testability. Search on Bibsonomy ITC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
18Abhijit Chatterjee, Jacob A. Abraham NCUBE: an automatic test generation program for iterative logic arrays. Search on Bibsonomy ICCAD The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
18Wu-Tung Cheng, Janak H. Patel Multiple-Fault Detection in Iterative Logic Arrays. Search on Bibsonomy ITC The full citation details ... 1985 DBLP  BibTeX  RDF
18Wu-Tung Cheng Testing and Error Detection in Iterative Logic Arrays Search on Bibsonomy 1985   RDF
18R. Parthasarathy, Sudhakar M. Reddy A Testable Design of Iterative Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1981 DBLP  DOI  BibTeX  RDF
18Premachandran R. Menon, Arthur D. Friedman Fault Detection in Iterative Logic Arrays. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1971 DBLP  DOI  BibTeX  RDF
15Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. Search on Bibsonomy VTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
15Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. Search on Bibsonomy J. Electron. Test. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF mutual checking, multiple signature testing, self loops, built-in self test, aliasing
10Chanyutt Arjhan, Raghvendra G. Deshmukh A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. Search on Bibsonomy Asian Test Symposium The full citation details ... 1999 DBLP  DOI  BibTeX  RDF parallel divider, parallel-array divider, pf-model, summand-generator, summand-counter, multiple faults functional testing, design for testability, boundary scan, array multiplier, Parallel multiplier
10Abhijit Chatterjee, Jacob A. Abraham Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. Search on Bibsonomy J. Electron. Test. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF Built-in self-test, test generation, design-for-testability, iterative logic array, pseudo-exhaustive test
10Y. You, John P. Hayes Implementation of VLSI self-testing by regularization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
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