Search results for "LUT-FPGAs"

Found 9 publication records. Showing 9 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
75	Artur Chojnacki, Lech Józwiak	High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures.	ISQED	2001	DBLP DOI BibTeX RDF
53	Igor Lemberski	Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
53	Uwe Hinsberger, Reiner Kolla	Optimal technology mapping for single output cells.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	optimal technology mapping, single output cells, DAG-mapping, minimum delay mapping, duplication-free mapping, logic duplication, AT-tradeoffs, LUT-FPGAs, field programmable gate arrays, delays, Boolean functions, Boolean functions, logic CAD, table lookup, cost functions, circuit optimisation, lookup table
26	Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi	In-Place Power Optimization for LUT-Based FPGAs.	DAC	1998	DBLP DOI BibTeX RDF
26	Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon	A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs.	ISPD	2021	DBLP DOI BibTeX RDF
26	Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini	An improved BCD adder using 6-LUT FPGAs.	NEWCAS	2012	DBLP DOI BibTeX RDF
26	Alexandre F. Tenca, Milos D. Ercegovac	Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size.	FPGA	1997	DBLP DOI BibTeX RDF
26	Narasimha B. Bhat, Dwight D. Hill	Routable Technologie Mapping for LUT FPGAs.	ICCD	1992	DBLP DOI BibTeX RDF
16	Takahiro Miomo, Koichi Yasuoka, Masanori Kanazawa	The Fastest Multiplier on FPGAs with Redundant Binary Representation.	FPL	2000	DBLP DOI BibTeX RDF

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