Search results for "Level-clocked"

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
107	Carl Ebeling, Brian Lockyear	On the performance of level-clocked circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	level-clocked circuits, level-sensitive latches, timing, synchronisation, flip-flops, clocks, retiming, clock skew, clock period, pipelined circuits
92	Naresh Maheshwari, Sachin S. Sapatnekar	Optimizing large multiphase level-clocked circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
80	Brian Lockyear, Carl Ebeling	Optimal retiming of level-clocked circuits using symmetric clock schedules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
60	Naresh Maheshwari, Sachin S. Sapatnekar	Efficient Minarea Retiming of Large Level-Clocked Circuits.	DATE	1998	DBLP DOI BibTeX RDF	Level-clocked, Optimization, Synthesis, Retiming, Area
60	Naresh Maheshwari, Sachin S. Sapatnekar	A Practical Algorithm for Retiming Level-Clocked Circuits.	ICCD	1996	DBLP DOI BibTeX RDF	level-clocked, retiming, clock skew, timing optimization
49	Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou	Optimizing two-phase, level-clocked circuitry.	J. ACM	1997	DBLP DOI BibTeX RDF	clock tuning, level-clocked circuitry, multiphase clocking, timing analysis and optimization, VLSI, retiming
35	Soha Hassoun, Christopher Cromer, Eduardo H. Calvillo Gámez	Static timing analysis for level-clocked circuits in the presence of crosstalk.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
23	Marios C. Papaefthymiou, Keith H. Randall	TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry.	DAC	1993	DBLP DOI BibTeX RDF

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