Search results for "MNA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai	Large scale RLC circuit analysis using RLCG-MNA formulation.	DATE	2006	DBLP DOI BibTeX RDF
53	Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai	Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation.	ISQED	2006	DBLP DOI BibTeX RDF
53	Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh	Simulation and sensitivity analysis of transmission line circuits by the characteristics method.	ICCAD	1996	DBLP DOI BibTeX RDF	simulation and sensitivity analysis, MNA equations, transmission lines, characteristics
51	Mohamed Khaled Ben Mna, Asma Ben Letaifa	Exploring the Impact of Speech AI: A Comparative Analysis of ML Models on Arabic Dataset.	ComNet	2023	DBLP DOI BibTeX RDF
40	Satoru Iwata 0001, Mizuyo Takamatsu	Index minimization of differential-algebraic equations in hybrid analysis for circuit simulation.	Math. Program.	2010	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 15A22, 34A09, 65L80, 68Q25
40	Raffi R. Kamalian, Alice M. Agogino, Hideyuki Takagi	Use of interactive evolutionary computation with simplified modeling for computationally expensive layout design optimization.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
40	Heinz Koeppl	The Composition Rule for Multivariate Volterra Operators and its Application to Circuit Analysis.	ISCAS	2007	DBLP DOI BibTeX RDF
40	Ajoy Opal	The transition matrix for linear circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
34	Giorgio Biagetti, Simone Orcioni, L. Signoracci, Claudio Turchetti, Paolo Crippa, Michele Alessandrini	SiSMA: a statistical simulator for mismatch analysis of MOS ICs.	ICCAD	2002	DBLP DOI BibTeX RDF	MNA, MOS ICs, device mismatch, non-Montecarlo analysis, stochastic simulation
33	Reza Hashemian	UaL Decomposition, an Alternative to the LU Factorization of MNA Matrices.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
33	Tom J. Smy, John H. Rasmussen	Integration of Traveling Wave Optical Device Models Into an MNA-Based Circuit Simulator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2020	DBLP DOI BibTeX RDF
33	Fatemehsadat Tabei, Rajnish Kumar, Tra Nguyen Phan, David D. McManus, Jo Woon Chong	A Novel Personalized Motion and Noise Artifact (MNA) Detection Method for Smartphone Photoplethysmograph (PPG) Signals.	IEEE Access	2018	DBLP DOI BibTeX RDF
33	Ali Bekir Yildiz	A Mna-Based Unified Ideal Switch Model for Analysis of Switching Circuits.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
33	Neena A. Gilda, Sheetal Patil, V. Seena, Sanjay Joshi, Viral Thaker, Sanket Thakur, Amaravati Anvesha, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao	Piezoresistive 6-MNA coated microcantilevers with signal conditioning circuits for electronic nose.	A-SSCC	2011	DBLP DOI BibTeX RDF
33	Akira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai	A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation.	ECCTD	2007	DBLP DOI BibTeX RDF
33	Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai	Generalized method of the time-domain circuit simulation based on LIM with MNA formulation.	CICC	2005	DBLP DOI BibTeX RDF
33	Diana Estévez Schwarz	A step-by-step approach to compute a consistent initialization for the MNA.	Int. J. Circuit Theory Appl.	2002	DBLP DOI BibTeX RDF
33	Diana Estévez Schwarz, Caren Tischendorf	Structural analysis of electric circuits and consequences for MNA.	Int. J. Circuit Theory Appl.	2000	DBLP DOI BibTeX RDF
33	Pawel Gburzynski, Jacek Maitan	Deflection Routing in Regular MNA Topologies.	J. High Speed Networks	1993	DBLP DOI BibTeX RDF
20	Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs	RDE-based transistor-level gate simulation for statistical static timing analysis.	DAC	2010	DBLP DOI BibTeX RDF	non-Monte Carlo, transistor-level modeling, statistical static timing analysis
20	Wenxuan Guo, Xinming Huang 0001	Mobility Model and Relay Management for Disaster Area Wireless Networks.	WASA	2008	DBLP DOI BibTeX RDF
20	Xiaoji Ye, Min Zhao 0001, Rajendran Panda, Peng Li 0001, Jiang Hu	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.	ISQED	2008	DBLP DOI BibTeX RDF	clock mesh, dynamic time step rounding, simulation, macromodel
20	Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan	Efficient Simulation of Power/Ground Networks with Package and Vias.	PATMOS	2005	DBLP DOI BibTeX RDF
20	Rong Jiang 0002, Charlie Chung-Ping Chen	Comprehensive frequency dependent interconnect extraction and evaluation methodology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam	A closed-form delay formula for on-chip RLC interconnects in current-mode signaling.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai	Interconnect model reductions by using the AORA algorithm with considering the adjoint network.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
20	Qin-Yu Zhu, Guang-Bin Huang, Chee Kheong Siew	A fast modular implementation for neural networks.	ICARCV	2004	DBLP DOI BibTeX RDF
20	Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen	SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation.	ICCAD	2003	DBLP DOI BibTeX RDF
20	Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng	Interconnect modeling and sensitivity analysis using adjoint networks reduction technique.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
20	Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh	Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Krylov, large scale systems, model reduction, RLC interconnects, balanced truncation
20	Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar	Passive model order reduction of multiport distributed interconnects.	DAC	2000	DBLP DOI BibTeX RDF