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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 32 publication records. Showing 31 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
53 | Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai |
Large scale RLC circuit analysis using RLCG-MNA formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 45-46, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai |
Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 393-400, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
53 | Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh |
Simulation and sensitivity analysis of transmission line circuits by the characteristics method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 556-562, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
simulation and sensitivity analysis, MNA equations, transmission lines, characteristics |
51 | Mohamed Khaled Ben Mna, Asma Ben Letaifa |
Exploring the Impact of Speech AI: A Comparative Analysis of ML Models on Arabic Dataset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ComNet ![In: Tenth IEEE International Conference on Communications and Networking, ComNet 2023, Hammamet, Tunisia, November 1-3, 2023, pp. 1-8, 2023, IEEE, 979-8-3503-8171-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
40 | Satoru Iwata 0001, Mizuyo Takamatsu |
Index minimization of differential-algebraic equations in hybrid analysis for circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Math. Program. ![In: Math. Program. 121(1), pp. 105-121, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classification (2000) 15A22, 34A09, 65L80, 68Q25 |
40 | Raffi R. Kamalian, Alice M. Agogino, Hideyuki Takagi |
Use of interactive evolutionary computation with simplified modeling for computationally expensive layout design optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 4124-4129, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Heinz Koeppl |
The Composition Rule for Multivariate Volterra Operators and its Application to Circuit Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 441-444, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Ajoy Opal |
The transition matrix for linear circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5), pp. 427-436, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
34 | Giorgio Biagetti, Simone Orcioni, L. Signoracci, Claudio Turchetti, Paolo Crippa, Michele Alessandrini |
SiSMA: a statistical simulator for mismatch analysis of MOS ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 490-496, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
MNA, MOS ICs, device mismatch, non-Montecarlo analysis, stochastic simulation |
33 | Reza Hashemian |
UaL Decomposition, an Alternative to the LU Factorization of MNA Matrices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(4), pp. 630-634, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
33 | Tom J. Smy, John H. Rasmussen |
Integration of Traveling Wave Optical Device Models Into an MNA-Based Circuit Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12), pp. 4338-4350, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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33 | Fatemehsadat Tabei, Rajnish Kumar, Tra Nguyen Phan, David D. McManus, Jo Woon Chong |
A Novel Personalized Motion and Noise Artifact (MNA) Detection Method for Smartphone Photoplethysmograph (PPG) Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 60498-60512, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
33 | Ali Bekir Yildiz |
A Mna-Based Unified Ideal Switch Model for Analysis of Switching Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(6), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
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33 | Neena A. Gilda, Sheetal Patil, V. Seena, Sanjay Joshi, Viral Thaker, Sanket Thakur, Amaravati Anvesha, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao |
Piezoresistive 6-MNA coated microcantilevers with signal conditioning circuits for electronic nose. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, South Korea, November 14-16, 2011, pp. 121-124, 2011, IEEE, 978-1-4577-1784-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
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33 | Akira Tsuzaki, Toshio Unno, Yuichi Tanji, Hideki Asai |
A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 18th European Conference on Circuit Theory and Design, ECCTD 2007, Seville, Spain, August 26-30, 2007, pp. 775-778, 2007, IEEE, 978-1-4244-1341-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
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33 | Hidemasa Kubota, Yuichi Tanji, Takayuki Watanabe, Hideki Asai |
Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, CICC 2005, DoubleTree Hotel, San Jose, California, USA, September 18-21, 2005, pp. 289-292, 2005, IEEE, 0-7803-9023-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Diana Estévez Schwarz |
A step-by-step approach to compute a consistent initialization for the MNA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 30(1), pp. 1-16, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Diana Estévez Schwarz, Caren Tischendorf |
Structural analysis of electric circuits and consequences for MNA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 28(2), pp. 131-162, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Pawel Gburzynski, Jacek Maitan |
Deflection Routing in Regular MNA Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. High Speed Networks ![In: J. High Speed Networks 2(2), pp. 99-131, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
20 | Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs |
RDE-based transistor-level gate simulation for statistical static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 787-792, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
non-Monte Carlo, transistor-level modeling, statistical static timing analysis |
20 | Wenxuan Guo, Xinming Huang 0001 |
Mobility Model and Relay Management for Disaster Area Wireless Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WASA ![In: Wireless Algorithms, Systems, and Applications, Third International Conference, WASA 2008, Dallas, TX, USA, October 26-28, 2008. Proceedings, pp. 274-285, 2008, Springer, 978-3-540-88581-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Xiaoji Ye, Min Zhao 0001, Rajendran Panda, Peng Li 0001, Jiang Hu |
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 627-632, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
clock mesh, dynamic time step rounding, simulation, macromodel |
20 | Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan |
Efficient Simulation of Power/Ground Networks with Package and Vias. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings, pp. 318-328, 2005, Springer, 3-540-29013-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Rong Jiang 0002, Charlie Chung-Ping Chen |
Comprehensive frequency dependent interconnect extraction and evaluation methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1070-1073, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Mingcui Zhou, Wentai Liu, Mohanasankar Sivaprakasam |
A closed-form delay formula for on-chip RLC interconnects in current-mode signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1082-1085, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai |
Interconnect model reductions by using the AORA algorithm with considering the adjoint network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1278-1281, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Qin-Yu Zhu, Guang-Bin Huang, Chee Kheong Siew |
A fast modular implementation for neural networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICARCV ![In: 8th International Conference on Control, Automation, Robotics and Vision, ICARCV 2004, Kunming, China, 6-9 December 2004, Proceedings, pp. 2270-2273, 2004, IEEE, 0-7803-8653-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen |
SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, pp. 786-792, 2003, IEEE Computer Society / ACM, 1-58113-762-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng |
Interconnect modeling and sensitivity analysis using adjoint networks reduction technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 648-651, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh |
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 311-316, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Krylov, large scale systems, model reduction, RLC interconnects, balanced truncation |
20 | Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar |
Passive model order reduction of multiport distributed interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 526-531, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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