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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 62 occurrences of 45 keywords
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Results
Found 708 publication records. Showing 707 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
179 | Xiangyu Dong, Xiaoxia Wu, Guangyu Sun 0003, Yuan Xie 0001, Hai Li 0001, Yiran Chen 0001 |
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 554-559, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
3D stacking, MRAM |
173 | Bruce F. Cockburn |
The Emergence of High-Density Semiconductor-Compatible Spintronic Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMENS ![In: 2003 International Conference on MEMS, NANO, and Smart Systems (ICMENS 2003), 20-23 July 2003, Banff, Alberta, Canada, pp. 321-326, 2003, IEEE Computer Society, 0-7695-1947-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
162 | Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat |
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(2), pp. 8:1-8:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Look-Up Table (LUT), MTJ, TAS, multi-context configuration, nonvolatile, Simulation, FPGA, architecture, low power, dynamical reconfiguration, flip-flop, MRAM |
156 | Bruce F. Cockburn |
Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 46-51, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
154 | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao |
Write Disturbance Modeling and Testing for MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(3), pp. 277-288, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
144 | Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu |
Fast identification of operating current for toggle MRAM by spiral search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 923-928, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
reliability, testing, BIST, characterization, yield enhancement, MRAM |
137 | Ethan L. Miller, Scott A. Brandt, Darrell D. E. Long |
HeRMES: High-Performance Reliable MRAM-Enabled Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HotOS ![In: Proceedings of HotOS-VIII: 8th Workshop on Hot Topics in Operating Systems, May 20-23, 2001, Elmau/Oberbayern, Germany, pp. 95-99, 2001, IEEE Computer Society, 0-7695-1040-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
120 | Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001 |
A novel architecture of the 3D stacked MRAM L2 cache for CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 239-249, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
120 | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu |
MRAM Defect Analysis and Fault Modeli. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 124-133, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
92 | Jing Li 0073, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy 0001 |
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 278-283, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
STT MRAM, yield |
75 | Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer |
Design of embedded MRAM macros for memory-in-logic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 155-158, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
thermally assisted switching (tas), architecture, low power, system on chip (soc), embedded, mram, non-volatile |
75 | Xiaochen Guo, Engin Ipek, Tolga Soyata |
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 371-382, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
STT-MRAM, power-efficiency |
75 | Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002 |
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 87-90, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
STT MRAM, defect tolerance, transistor sizing |
69 | Mike Mannion, Hermann Kaindl |
Requirements-based product line engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESEC / SIGSOFT FSE ![In: Proceedings of the 8th European Software Engineering Conference held jointly with 9th ACM SIGSOFT International Symposium on Foundations of Software Engineering 2001, Vienna, Austria, September 10-14, 2001, pp. 322-323, 2001, ACM, 978-1-58113-390-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
reuse, requirements, variability, product line engineering |
68 | Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu |
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 19-22 May 2004, Toronto, Canada, pp. 340-345, 2004, IEEE Computer Society, 0-7695-2130-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
56 | Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli |
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings, pp. 18-23, 2009, IEEE Computer Society, 978-0-7695-3917-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Dynamic Reconfiguration, MRAM, non volatility |
52 | Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune |
A non-volatile run-time FPGA using thermally assisted switching MRAMS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 421-426, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
52 | Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi |
A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 507-515, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Mram Kahla, Zijian Gyozo Yang, Attila Novák |
Cross-lingual Fine-tuning for Abstractive Arabic Text Summarization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RANLP ![In: Proceedings of the International Conference on Recent Advances in Natural Language Processing (RANLP 2021), Held Online, 1-3 September, 2021, pp. 655-663, 2021, INCOMA Ltd.. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
50 | Frank Wang |
A modified architecture for high-density MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 29(1), pp. 16-22, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
computer data storage, nonvolatility, parallel operation, storage density, random access memory |
42 | Betty Prince |
Embedded non-volatile memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 9, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM |
42 | Betty Prince |
Nanotechnology and emerging memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 4, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory |
35 | Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim |
An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 877-882, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Jing Li 0073, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy 0001 |
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 841-846, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa |
MRAM Write Error Categorization with QCKB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 43-48, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Edward K. S. Au, Wing-Hung Ki, Wai Ho Mow, Silas T. Hung, Catherine Y. Wong |
A binary--search switched--current sensing scheme for 4-state MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 304-307, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
magneto-resistive random access memory, switched-current |
33 | Tetsuya Uemura, Masafumi Yamamoto |
Proposal of Four-Valued MRAM based on MTJ/RTD Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan, pp. 273-280, 2003, IEEE Computer Society, 0-7695-1918-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Ruili Zhang, William C. Black Jr., Marwan M. Hassoun |
Windowed MRAM Sensing Scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, pp. 47-58, 2000, IEEE Computer Society, 0-7695-0689-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
32 | Farah Ferdaus, Bashir Mohammad Sabquat Bahar Talukder, Md. Tauhidur Rahman 0001 |
Approximate MRAM: High-Performance and Power-Efficient Computing With MRAM Chips for Error-Tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(3), pp. 668-681, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
32 | Haris Suhail, Jiyue Yang, Haoran He, Kang L. Wang, Sudhakar Pamarti |
Analytical Array-Level Comparison of Read/Write Performance Between Voltage Controlled-MRAM and STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 326-330, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
32 | Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou |
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
32 | Loïc France |
Development and evaluation of solutions for the protection of DRAM and MRAM memories against Rowhammer attacks. (Développement et évaluation de solutions de protections des DRAM et MRAM contre l'attaque Rowhammer). ![Search on Bibsonomy](Pics/bibsonomy.png) |
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2022 |
RDF |
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32 | Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Md. Tauhidur Rahman 0001 |
Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2105.14151, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
32 | Barry Hoberman, Jean-Pierre Nozieres |
SOT-MRAM - Third generation MRAM memory opens new opportunities : Hot Chips Conference August 2021. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HCS ![In: IEEE Hot Chips 33 Symposium, HCS 2021, Palo Alto, CA, USA, August 22-24, 2021, pp. 1-10, 2021, IEEE, 978-1-6654-1397-8. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
32 | Mounia Kharbouche-Harrari |
Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l'internet des Objets. (CMOS/STT-MRAM hybridization of integrated circuits for the hardware security of the Internet of Things). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
32 | Jayita Das, Kevin Scott, Sanjukta Bhanja |
MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 13(1), pp. 2:1-2:15, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
32 | Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura |
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013, pp. 1813-1818, 2013, EDA Consortium San Jose, CA, USA / ACM DL, 978-1-4503-2153-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
32 | Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung |
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 20(1), pp. 181-186, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
32 | William J. Gallagher, Stuart S. P. Parkin |
Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBM J. Res. Dev. ![In: IBM J. Res. Dev. 50(1), pp. 5-24, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Erwin J. Prinz |
The zen of nonvolatile memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 815-820, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FeRAM, SONOS, nanocrystal, oating gate, phase change memory, MRAM, nonvolatile memories |
17 | In Hwan Doh, Young Jin Kim, Jung Soo Park, Eunsam Kim, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh |
Towards greener data centers with storage class memory: minimizing idle power waste through coarse-grain management in fine-grain scale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 309-318, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
non-volatile ram (nvram), storage class memory (scm), power management, servers |
17 | Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001 |
Hybrid cache architecture with disparate memory technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 34-45, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
hybrid cache architecture, three-dimensional ic |
17 | Y. Hosogaya, Toshio Endo, Satoshi Matsuoka |
Performance evaluation of parallel applications on next generation memory architecture with power-aware paging method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | William Enck, Kevin R. B. Butler, Thomas Richardson, Patrick D. McDaniel, Adam D. Smith |
Defending Against Attacks on Main Memory Persistence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: Twenty-Fourth Annual Computer Security Applications Conference, ACSAC 2008, Anaheim, California, USA, 8-12 December 2008, pp. 65-74, 2008, IEEE Computer Society, 978-0-7695-3447-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro |
A low-SER efficient core processor architecture for future technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 1448-1453, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | In Hwan Doh, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh |
Exploiting non-volatile RAM to enhance flash file system performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 7th ACM & IEEE International conference on Embedded software, EMSOFT 2007, September 30 - October 3, 2007, Salzburg, Austria, pp. 164-173, 2007, ACM, 978-1-59593-825-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-volatile RAM, metadata, file system, flash memory, experimental evaluation |
17 | Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto |
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 49, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Michael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gary H. Bernstein, Wolfgang Porod, M. Putney, J. DeAngelis |
Clocking structures and power analysis for nanomagnet-based logic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 26-31, 2007, ACM, 978-1-59593-709-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
magnetic logic, nanotechnology, clocking, QCA |
17 | Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon |
New non-volatile FPGA concept using Magnetic Tunneling Junction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 269-276, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon |
Magnetic tunnelling junction based FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006, pp. 123-130, 2006, ACM, 1-59593-292-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
magnetic tunneling junction, FPGA, non volatility |
17 | Feng Wang 0003, Bo Hong, Scott A. Brandt, Darrell D. E. Long |
Using MEMS-Based Storage to Boost Disk Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSST ![In: 22nd IEEE / 13th NASA Goddard Conference on Mass Storage Systems and Technologies (MSST 2005), Information Retrieval from Very Large Storage Systems, CD-ROM, 11-14 April 2005, Monterey, CA, USA, pp. 202-209, 2005, IEEE Computer Society, 0-7695-2318-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Frank Bellosa |
When physical is not real enough. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS European Workshop ![In: Proceedings of the 11st ACM SIGOPS European Workshop, Leuven, Belgium, September 19-22, 2004, pp. 25, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk |
Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings, pp. 347-355, 2004, IEEE Computer Society, 0-7695-2241-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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16 | Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi 0001 |
A Case Study for Improving Performances of Deep-Learning Processor with MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSJ Trans. Syst. LSI Des. Methodol. ![In: IPSJ Trans. Syst. LSI Des. Methodol. 17, pp. 7-15, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang |
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(1), pp. 219-230, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono |
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 59(4), pp. 1283-1292, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | H. D. Kallinatha, Sadhana Rai, Basavaraj Talawar |
A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 7224-7243, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Ivan Fernandez, Christina Giannoula, Aditya Manglik, Ricardo Quislant, Nika Mansouri-Ghiasi, Juan Gómez-Luna, Eladio Gutiérrez, Oscar G. Plata, Onur Mutlu |
MATSA: An MRAM-Based Energy-Efficient Accelerator for Time Series Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 36727-36742, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Belal Jahannia, Seyed Ali Ghasemi, Hamed Farbeh |
Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 26562-26580, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Alaba Yusuf, Tosiron Adegbija, Dhruv Gajaria |
Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 28036-28056, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo |
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 32(2), pp. 245-255, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu 0008, Deming Zhang, Xiangshui Miao |
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 32(3), pp. 497-504, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Jia-Le Cui, Yanan Guo 0004, Juntong Chen, Bo Liu 0019, Hao Cai |
Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 12(1), pp. 97-108, January - March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu |
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(1), pp. 187-200, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Chao Wang 0094, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang |
Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1651-1664, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang 0011, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang 0001 |
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(3), pp. 1130-1143, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Zhongzhen Tong, Yilin Xu, Yunlong Liu, Xinrui Duan, Hao Tang, Suteng Zhao, Chenghang Li, Zhiting Lin, Xiulong Wu, Zhaohao Wang, Xiaoyang Lin |
A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(2), pp. 606-619, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Jinkai Wang, Zhengkun Gu, Bojun Zhang, Youxiang Chen, Zekun Wang, Kun Zhang 0030, Youguang Zhang, Yue Zhang 0010 |
RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(3), pp. 1014-1024, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Haotian Fu, Yulong Huang, Tingran Chen, Chenyi Fu, Hongwei Ren, Yue Zhou, Shouzhong Peng, Zhirui Zong, Biao Pan, Bojun Cheng |
DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(4), pp. 1638-1650, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Belal Jahannia, Seyed Ali Ghasemi, Hamed Farbeh |
An Energy Efficient Multi-Retention STT-MRAM Memory Architecture for IoT Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(3), pp. 1431-1435, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Haoran Du, You Wang 0002, Jun Yang 0006, Hao Cai |
Intrinsic MRAM Properties Enable Security Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(3), pp. 1695-1700, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | YaJuan Hui, Qingzhen Li, Cheng Liu 0008, Deming Zhang, Xiangshui Miao |
Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(4), pp. 2309-2313, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Chao Wang 0094, Zhaohao Wang, Zhongkui Zhang, Youguang Zhang, Weisheng Zhao |
Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 71(3), pp. 1386-1390, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
16 | Kaniz Mishty, Mehdi Sadi |
System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4), pp. 1065-1078, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Yu Gu, Puyang Huang, Tianhao Chen, Chenyi Fu, Aitian Chen, Shouzhong Peng, Xixiang Zhang, Xufeng Kou |
A noise-tolerant, resource-saving probabilistic binary neural network implemented by the SOT-MRAM compute-in-memory system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2403.19374, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang |
15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 292-294, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono |
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, pp. 290-292, 2024, IEEE, 979-8-3503-0620-0. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
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16 | Tatiana Moposita, Esteban Garzón, Raffaele De Rose, Felice Crupi, Andrei Vladimirescu, Lionel Trojman, Marco Lanuzza |
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 144084-144094, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Yongwoon Song, Munhyung Lee, Hyukjun Lee |
High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 11, pp. 98016-98024, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh |
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(7), pp. 1078-1082, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Shaopu Han, Yanfeng Jiang |
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(7), pp. 980-992, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh |
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 31(6), pp. 906, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao |
A Survey of MRAM-Centric Computing: From Near Memory to In Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(2), pp. 318-330, April - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Arash Salahvarzi, Mohsen Khosroanjam, Amir Mahdi Hosseini Monazzah, Hakem Beitollahi, Ümit Y. Ogras, Mahdi Fazeli |
WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(1), pp. 43-55, January - March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Shadi Sheikhfaal, Shaahin Angizi, Ronald F. DeMara |
Energy-Efficient Recurrent Neural Network With MRAM-Based Probabilistic Activation Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(2), pp. 534-540, April - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Bi Wu, Haonan Zhu, Ke Chen 0018, Chenggang Yan 0002, Weiqiang Liu 0001 |
MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(6), pp. 2412-2424, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | An Yang, Zhilin Jiang, Zheng Huang, Zitong Zhang, Yanfeng Jiang |
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 70(3), pp. 1147-1160, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Xunming Zhang, Long Liu, Di Wang, Ruijun Lin, Heyong Yang, Xiaoxin Xu, Jianguo Yang, Guozhong Xing, Xiaoyong Xue, Xiaoyang Zeng |
Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2226-2230, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Enlong Liu, Kunkun Li, Ao Shen, Shikun He |
Area and Energy Efficient SOT-MRAM Bit Cell Based on 3 Transistors With Shared Diffusion Regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2206-2210, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Taehui Na |
Ternary Output Binary Neural Network With Zero-Skipping for MRAM-Based Digital In-Memory Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(7), pp. 2655-2659, July 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Alok Kumar Shukla, Sandeep Soni, Brajesh Kumar Kaushik |
Novel Radiation Hardened DSOT-MRAM Read Peripheral Circuit With Reduced Sensitive Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(11), pp. 4236-4240, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge |
Rethinking DRAM's Page Mode With STT-MRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 72(5), pp. 1503-1517, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Wei Zhao 0034, Dan Feng 0001, Wei Tong 0001, Jingning Liu, Zhangyu Chen, Bing Wu 0001, Chengning Wang |
APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11), pp. 3840-3853, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Chao Wang 0094, Zhaohao Wang, Zhongkui Zhang, Jiagao Feng, Youguang Zhang, Weisheng Zhao |
Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5), pp. 1463-1476, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Wei Zhao 0034, Jie Xu 0013, Xueliang Wei, Bing Wu 0001, Chengning Wang, Weilin Zhu, Wei Tong 0001, Dan Feng 0001, Jingning Liu |
A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1), pp. 122-135, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Yinglin Zhao, Jianlei Yang 0001, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao |
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 66(4), April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Yueting Li, Wang Kang 0001, Kunyu Zhou, Keni Qiu, Weisheng Zhao |
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 22(2), pp. 29:1-29:24, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Sourjya Roy, Cheng Wang, Anand Raghunathan |
Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2308.02024, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Kaniz Mishty, Mehdi Sadi |
System and Design Technology Co-optimization of SOT-MRAM for High-Performance AI Accelerator Memory System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.12310, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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16 | Arpan Suravi Prasad, Moritz Scherer, Francesco Conti 0001, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini |
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.14750, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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