Search results for "MRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
179	Xiangyu Dong, Xiaoxia Wu, Guangyu Sun 0003, Yuan Xie 0001, Hai Li 0001, Yiran Chen 0001	Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.	DAC	2008	DBLP DOI BibTeX RDF	3D stacking, MRAM
173	Bruce F. Cockburn	The Emergence of High-Density Semiconductor-Compatible Spintronic Memory.	ICMENS	2003	DBLP DOI BibTeX RDF
162	Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat	TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Look-Up Table (LUT), MTJ, TAS, multi-context configuration, nonvolatile, Simulation, FPGA, architecture, low power, dynamical reconfiguration, flip-flop, MRAM
156	Bruce F. Cockburn	Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory.	MTDT	2004	DBLP DOI BibTeX RDF
154	Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao	Write Disturbance Modeling and Testing for MRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
144	Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu	Fast identification of operating current for toggle MRAM by spiral search.	DAC	2010	DBLP DOI BibTeX RDF	reliability, testing, BIST, characterization, yield enhancement, MRAM
137	Ethan L. Miller, Scott A. Brandt, Darrell D. E. Long	HeRMES: High-Performance Reliable MRAM-Enabled Storage.	HotOS	2001	DBLP DOI BibTeX RDF
120	Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Jian Li 0059, Yiran Chen 0001	A novel architecture of the 3D stacked MRAM L2 cache for CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
120	Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu	MRAM Defect Analysis and Fault Modeli.	ITC	2004	DBLP DOI BibTeX RDF
92	Jing Li 0073, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy 0001	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.	DAC	2008	DBLP DOI BibTeX RDF	STT MRAM, yield
75	Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer	Design of embedded MRAM macros for memory-in-logic applications.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	thermally assisted switching (tas), architecture, low power, system on chip (soc), embedded, mram, non-volatile
75	Xiaochen Guo, Engin Ipek, Tolga Soyata	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.	ISCA	2010	DBLP DOI BibTeX RDF	STT-MRAM, power-efficiency
75	Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.	DAC	2009	DBLP DOI BibTeX RDF	STT MRAM, defect tolerance, transistor sizing
69	Mike Mannion, Hermann Kaindl	Requirements-based product line engineering.	ESEC / SIGSOFT FSE	2001	DBLP DOI BibTeX RDF	reuse, requirements, variability, product line engineering
68	Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu	A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices.	ISMVL	2004	DBLP DOI BibTeX RDF
56	Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli	MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs.	ReConFig	2009	DBLP DOI BibTeX RDF	FPGA, Dynamic Reconfiguration, MRAM, non volatility
52	Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune	A non-volatile run-time FPGA using thermally assisted switching MRAMS.	FPL	2008	DBLP DOI BibTeX RDF
52	Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi	A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory.	DFT	2008	DBLP DOI BibTeX RDF
51	Mram Kahla, Zijian Gyozo Yang, Attila Novák	Cross-lingual Fine-tuning for Abstractive Arabic Text Summarization.	RANLP	2021	DBLP BibTeX RDF
50	Frank Wang	A modified architecture for high-density MRAM.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	computer data storage, nonvolatility, parallel operation, storage density, random access memory
42	Betty Prince	Embedded non-volatile memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, MONOS, PC-RAM, SONOS, floating gate memory, nanocrystal memory, nitride storage memory, trapping site memory, flash memory, embedded memory, non-volatile memory, MRAM
42	Betty Prince	Nanotechnology and emerging memories.	SBCCI	2007	DBLP DOI BibTeX RDF	FeRAM, ferroelectric, floating body, nanocrystal, nitride storage, scaling issues, single electron memories, memory, variability, scaling, SRAM, MEMs, DRAM, flash, MRAM, phase change, non-volatile, molecular memory
35	Jong-Chul Lim, Hye-Seung Yu, Jae-Suk Choi, Soo-Won Kim	An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin.	ASP-DAC	2005	DBLP DOI BibTeX RDF
33	Jing Li 0073, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy 0001	An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.	ASP-DAC	2009	DBLP DOI BibTeX RDF
33	Yuui Shimizu, Hisanori Aikawa, Keiji Hosotani, Naoharu Shimomura, Tadashi Kai, Yoshihiro Ueda, Yoshiaki Asao, Yoshihisa Iwata, Kenji Tsuchida, Sumio Ikegawa	MRAM Write Error Categorization with QCKB.	MTDT	2006	DBLP DOI BibTeX RDF
33	Edward K. S. Au, Wing-Hung Ki, Wai Ho Mow, Silas T. Hung, Catherine Y. Wong	A binary--search switched--current sensing scheme for 4-state MRAM.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	magneto-resistive random access memory, switched-current
33	Tetsuya Uemura, Masafumi Yamamoto	Proposal of Four-Valued MRAM based on MTJ/RTD Structure.	ISMVL	2003	DBLP DOI BibTeX RDF
33	Ruili Zhang, William C. Black Jr., Marwan M. Hassoun	Windowed MRAM Sensing Scheme.	MTDT	2000	DBLP DOI BibTeX RDF
32	Farah Ferdaus, Bashir Mohammad Sabquat Bahar Talukder, Md. Tauhidur Rahman 0001	Approximate MRAM: High-Performance and Power-Efficient Computing With MRAM Chips for Error-Tolerant Applications.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
32	Haris Suhail, Jiyue Yang, Haoran He, Kang L. Wang, Sudhakar Pamarti	Analytical Array-Level Comparison of Read/Write Performance Between Voltage Controlled-MRAM and STT-MRAM.	MWSCAS	2023	DBLP DOI BibTeX RDF
32	Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-Jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou	U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
32	Loïc France	Development and evaluation of solutions for the protection of DRAM and MRAM memories against Rowhammer attacks. (Développement et évaluation de solutions de protections des DRAM et MRAM contre l'attaque Rowhammer).		2022	RDF
32	Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Md. Tauhidur Rahman 0001	Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications.	CoRR	2021	DBLP BibTeX RDF
32	Barry Hoberman, Jean-Pierre Nozieres	SOT-MRAM - Third generation MRAM memory opens new opportunities : Hot Chips Conference August 2021.	HCS	2021	DBLP DOI BibTeX RDF
32	Mounia Kharbouche-Harrari	Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l'internet des Objets. (CMOS/STT-MRAM hybridization of integrated circuits for the hardware security of the Internet of Things).		2019	RDF
32	Jayita Das, Kevin Scott, Sanjukta Bhanja	MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells.	ACM J. Emerg. Technol. Comput. Syst.	2016	DBLP DOI BibTeX RDF
32	Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura	D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory.	DATE	2013	DBLP DOI BibTeX RDF
32	Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung	A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM).	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
32	William J. Gallagher, Stuart S. P. Parkin	Development of the magnetic tunnel junction MRAM at IBM: From first junctions to a 16-Mb MRAM demonstrator chip.	IBM J. Res. Dev.	2006	DBLP DOI BibTeX RDF
25	Erwin J. Prinz	The zen of nonvolatile memories.	DAC	2006	DBLP DOI BibTeX RDF	FeRAM, SONOS, nanocrystal, oating gate, phase change memory, MRAM, nonvolatile memories
17	In Hwan Doh, Young Jin Kim, Jung Soo Park, Eunsam Kim, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh	Towards greener data centers with storage class memory: minimizing idle power waste through coarse-grain management in fine-grain scale.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	non-volatile ram (nvram), storage class memory (scm), power management, servers
17	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
17	Y. Hosogaya, Toshio Endo, Satoshi Matsuoka	Performance evaluation of parallel applications on next generation memory architecture with power-aware paging method.	IPDPS	2008	DBLP DOI BibTeX RDF
17	William Enck, Kevin R. B. Butler, Thomas Richardson, Patrick D. McDaniel, Adam D. Smith	Defending Against Attacks on Main Memory Persistence.	ACSAC	2008	DBLP DOI BibTeX RDF
17	Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa, Luigi Carro	A low-SER efficient core processor architecture for future technologies.	DATE	2007	DBLP DOI BibTeX RDF
17	In Hwan Doh, Jongmoo Choi, Donghee Lee 0001, Sam H. Noh	Exploiting non-volatile RAM to enhance flash file system performance.	EMSOFT	2007	DBLP DOI BibTeX RDF	non-volatile RAM, metadata, file system, flash memory, experimental evaluation
17	Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto	Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions.	ISMVL	2007	DBLP DOI BibTeX RDF
17	Michael T. Niemier, M. Alam, Xiaobo Sharon Hu, Gary H. Bernstein, Wolfgang Porod, M. Putney, J. DeAngelis	Clocking structures and power analysis for nanomagnet-based logic devices.	ISLPED	2007	DBLP DOI BibTeX RDF	magnetic logic, nanotechnology, clocking, QCA
17	Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon	New non-volatile FPGA concept using Magnetic Tunneling Junction.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon	Magnetic tunnelling junction based FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	magnetic tunneling junction, FPGA, non volatility
17	Feng Wang 0003, Bo Hong, Scott A. Brandt, Darrell D. E. Long	Using MEMS-Based Storage to Boost Disk Performance.	MSST	2005	DBLP DOI BibTeX RDF
17	Frank Bellosa	When physical is not real enough.	ACM SIGOPS European Workshop	2004	DBLP DOI BibTeX RDF
17	John Y. Fong, Randy Acklin, John Roscher, Feng Li, Cindy Laird, Cezary Pietrzyk	Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories.	DFT	2004	DBLP DOI BibTeX RDF
16	Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi 0001	A Case Study for Improving Performances of Deep-Learning Processor with MRAM.	IPSJ Trans. Syst. LSI Des. Methodol.	2024	DBLP DOI BibTeX RDF
16	De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang	An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
16	Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono	A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
16	H. D. Kallinatha, Sadhana Rai, Basavaraj Talawar	A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment.	IEEE Access	2024	DBLP DOI BibTeX RDF
16	Ivan Fernandez, Christina Giannoula, Aditya Manglik, Ricardo Quislant, Nika Mansouri-Ghiasi, Juan Gómez-Luna, Eladio Gutiérrez, Oscar G. Plata, Onur Mutlu	MATSA: An MRAM-Based Energy-Efficient Accelerator for Time Series Analysis.	IEEE Access	2024	DBLP DOI BibTeX RDF
16	Belal Jahannia, Seyed Ali Ghasemi, Hamed Farbeh	Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes.	IEEE Access	2024	DBLP DOI BibTeX RDF
16	Alaba Yusuf, Tosiron Adegbija, Dhruv Gajaria	Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey.	IEEE Access	2024	DBLP DOI BibTeX RDF
16	Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo	Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu 0008, Deming Zhang, Xiangshui Miao	In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
16	Jia-Le Cui, Yanan Guo 0004, Juntong Chen, Bo Liu 0019, Hao Cai	Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference.	IEEE Trans. Emerg. Top. Comput.	2024	DBLP DOI BibTeX RDF
16	Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu	A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
16	Chao Wang 0094, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang	Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
16	Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang 0011, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang 0001	CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
16	Zhongzhen Tong, Yilin Xu, Yunlong Liu, Xinrui Duan, Hao Tang, Suteng Zhao, Chenghang Li, Zhiting Lin, Xiulong Wu, Zhaohao Wang, Xiaoyang Lin	A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
16	Jinkai Wang, Zhengkun Gu, Bojun Zhang, Youxiang Chen, Zekun Wang, Kun Zhang 0030, Youguang Zhang, Yue Zhang 0010	RSACIM: Resistance Summation Analog Computing in Memory With Accuracy Optimization Scheme Based on MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
16	Haotian Fu, Yulong Huang, Tingran Chen, Chenyi Fu, Hongwei Ren, Yue Zhou, Shouzhong Peng, Zhirui Zong, Biao Pan, Bojun Cheng	DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
16	Belal Jahannia, Seyed Ali Ghasemi, Hamed Farbeh	An Energy Efficient Multi-Retention STT-MRAM Memory Architecture for IoT Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	Haoran Du, You Wang 0002, Jun Yang 0006, Hao Cai	Intrinsic MRAM Properties Enable Security Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	YaJuan Hui, Qingzhen Li, Cheng Liu 0008, Deming Zhang, Xiangshui Miao	Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	Chao Wang 0094, Zhaohao Wang, Zhongkui Zhang, Youguang Zhang, Weisheng Zhao	Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
16	Kaniz Mishty, Mehdi Sadi	System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
16	Yu Gu, Puyang Huang, Tianhao Chen, Chenyi Fu, Aitian Chen, Shouzhong Peng, Xixiang Zhang, Xufeng Kou	A noise-tolerant, resource-saving probabilistic binary neural network implemented by the SOT-MRAM compute-in-memory system.	CoRR	2024	DBLP DOI BibTeX RDF
16	Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang	15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes.	ISSCC	2024	DBLP DOI BibTeX RDF
16	Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono	15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.	ISSCC	2024	DBLP DOI BibTeX RDF
16	Tatiana Moposita, Esteban Garzón, Raffaele De Rose, Felice Crupi, Andrei Vladimirescu, Lionel Trojman, Marco Lanuzza	SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Yongwoon Song, Munhyung Lee, Hyukjun Lee	High Bandwidth and Highly Available Packet Buffer Design Using Multi-Retention Time MRAM.	IEEE Access	2023	DBLP DOI BibTeX RDF
16	Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh	Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Shaopu Han, Yanfeng Jiang	RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh	Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
16	Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao	A Survey of MRAM-Centric Computing: From Near Memory to In Memory.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
16	Arash Salahvarzi, Mohsen Khosroanjam, Amir Mahdi Hosseini Monazzah, Hakem Beitollahi, Ümit Y. Ogras, Mahdi Fazeli	WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
16	Shadi Sheikhfaal, Shaahin Angizi, Ronald F. DeMara	Energy-Efficient Recurrent Neural Network With MRAM-Based Probabilistic Activation Functions.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
16	Bi Wu, Haonan Zhu, Ke Chen 0018, Chenggang Yan 0002, Weiqiang Liu 0001	MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
16	An Yang, Zhilin Jiang, Zheng Huang, Zitong Zhang, Yanfeng Jiang	Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
16	Xunming Zhang, Long Liu, Di Wang, Ruijun Lin, Heyong Yang, Xiaoxin Xu, Jianguo Yang, Guozhong Xing, Xiaoyong Xue, Xiaoyang Zeng	Area-Efficient 1T-2D-2MTJ SOT-MRAM Cell for High Read Performance.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Enlong Liu, Kunkun Li, Ao Shen, Shikun He	Area and Energy Efficient SOT-MRAM Bit Cell Based on 3 Transistors With Shared Diffusion Regions.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Taehui Na	Ternary Output Binary Neural Network With Zero-Skipping for MRAM-Based Digital In-Memory Computing.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Alok Kumar Shukla, Sandeep Soni, Brajesh Kumar Kaushik	Novel Radiation Hardened DSOT-MRAM Read Peripheral Circuit With Reduced Sensitive Nodes.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
16	Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge	Rethinking DRAM's Page Mode With STT-MRAM.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
16	Wei Zhao 0034, Dan Feng 0001, Wei Tong 0001, Jingning Liu, Zhangyu Chen, Bing Wu 0001, Chengning Wang	APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Chao Wang 0094, Zhaohao Wang, Zhongkui Zhang, Jiagao Feng, Youguang Zhang, Weisheng Zhao	Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Wei Zhao 0034, Jie Xu 0013, Xueliang Wei, Bing Wu 0001, Chengning Wang, Weilin Zhu, Wei Tong 0001, Dan Feng 0001, Jingning Liu	A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
16	Yinglin Zhao, Jianlei Yang 0001, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao	NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.	Sci. China Inf. Sci.	2023	DBLP DOI BibTeX RDF
16	Yueting Li, Wang Kang 0001, Kunyu Zhou, Keni Qiu, Weisheng Zhao	Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
16	Sourjya Roy, Cheng Wang, Anand Raghunathan	Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators.	CoRR	2023	DBLP DOI BibTeX RDF
16	Kaniz Mishty, Mehdi Sadi	System and Design Technology Co-optimization of SOT-MRAM for High-Performance AI Accelerator Memory System.	CoRR	2023	DBLP DOI BibTeX RDF
16	Arpan Suravi Prasad, Moritz Scherer, Francesco Conti 0001, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini	Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine.	CoRR	2023	DBLP DOI BibTeX RDF