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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 63 occurrences of 44 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
110 | Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko, I. Bondar |
Technique of Computing Logic Derivatives for MVL-Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 267-272, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
logic derivatives, partial direct, inverse derivatives, matrix approach, MVL switching circuit, truth vectors, multivalued logic, logic processing, MVL-functions |
96 | Zheng Tang, Okihiko Ishizuka, Koichi Tanno |
Learning Multiple-Valued Logic Networks Based on Back Propagation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 270-275, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued logic networks learning, canonical realization, initial parameters, neural nets, simulation results, backpropagation, backpropagation, multivalued logic, parameter space, functional completeness |
84 | Hui Min Wang, Chung-Len Lee 0001, Jwu E. Chen |
Factorization of Multi-Valued Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 164-169, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multi-valued logic function factorization, multi valued logic functions, rectangular covering problem, MVL algebraic factorization algorithm, MVL Boolean properties, purely algebraic factorization algorithm, multilevel implementation, Boolean method, MVL example functions, computational complexity, complexity, Boolean functions, multivalued logic |
83 | Arkadij Zakrevskij, Lev Zakrevski |
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 61-65, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
78 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan, G. A. Hamid |
On the Synthesis of MVL Functions Using Input and Output Phase Assignments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 253-258, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic |
75 | Christian Lang 0001, Bernd Steinbach |
Bi-Decomposition of Function Sets in Multiple-Valued Logic for Circuit Design and Data Mining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Artif. Intell. Rev. ![In: Artif. Intell. Rev. 20(3-4), pp. 233-267, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
bi-decomposition, differential calculus, multi-level circuit design, data mining, machine learning, logic synthesis, multiple-valued logic |
67 | Mitchell A. Thornton |
Spectral Transforms of Mixed-radix MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 16-19 May 2003, Tokyo, Japan, pp. 329-333, 2003, IEEE Computer Society, 0-7695-1918-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
66 | Mostafa I. H. Abd-El-Barr, Bambang A. B. Sarif |
Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, 13-16 May 2007, Oslo, Norway, pp. 48, 2007, IEEE Computer Society, 978-0-7695-2831-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
59 | Craig M. Files, Rolf Drechsler, Marek A. Perkowski |
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 27-34, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
learning samples, minterms, machine learning, learning (artificial intelligence), minimization, functional decomposition, multi-valued logic, multi-valued decision diagrams, problem complexity, MVL functions |
59 | Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky |
Algorithmic Synthesis of MVL Functions for CCD Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(8), pp. 977-986, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
algorithmic synthesis, CCD implementation, sum of products, logic design, many-valued logics, logic circuits, charge-coupled devices, MVL functions, literals |
52 | Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic |
Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 265-272, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
multiple-valued logic functions, information theory measures, decision trees, minimization |
52 | Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan |
New MVL-PLA Structures Based on Current-Mode CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 98-103, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic |
35 | Ugur Kalay, Marek A. Perkowski, Douglas V. Hall |
Highly Testable Boolean Ring Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 268-274, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits |
35 | Zeljko Zilic, Zvonko G. Vranesic |
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 26th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings, pp. 16-23, 1996, IEEE Computer Society, 0-8186-7392-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
35 | A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton |
Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 216-221, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function |
33 | Anna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko |
The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), May 15-18, 2002, Boston, Massachusetts, USA, pp. 209-215, 2002, IEEE Computer Society, 0-7695-1462-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
multiple-valued logic circuits, word-level decision diagrams |
33 | Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic |
Generic Implementation of DD Packages in MVL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 25th EUROMICRO '99 Conference, Informatics: Theory and Practice for the New Millenium, 8-10 September 1999, Milan, Italy, pp. 1352-1359, 1999, IEEE Computer Society, 0-7695-0321-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Gregory E. Beers, Lizy Kurian John |
Novel Memory Bus Driver/Receiver Architecture for Higher Throughput. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 259-264, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
31 | Bambang A. B. Sarif, Mostafa I. H. Abd-El-Barr |
The Use of Multiple Connected Pseudo Minterms in the Synthesis of MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan, pp. 145-150, 2009, IEEE Computer Society, 978-0-7695-3607-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
31 | Mitchell A. Thornton |
The Karhunen-Loève Transform of Discrete MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 18-21 May 2005, Calgary, Canada, pp. 194-199, 2005, IEEE Computer Society, 0-7695-2336-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Mostafa I. H. Abd-El-Barr, H. Choy |
Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 22nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1992, Sendai, Japan, May 27-29, 1992, Proceedings, pp. 111-118, 1992, IEEE Computer Society, 0-8186-2680-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Mostafa I. H. Abd-El-Barr, M. I. Mahroos |
On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 22nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 1992, Sendai, Japan, May 27-29, 1992, Proceedings, pp. 221-228, 1992, IEEE Computer Society, 0-8186-2680-1. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
31 | Safwat G. Zaky, Zvonko G. Vranesic, Mostafa I. H. Abd-El-Barr |
Step-Wise Synthesis of CCD MVL Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: Proceedings of the 20th International Symposium on Multiple-Valued Logic, ISMVL 1990, Charlotte, NC, USA, May 23-25, 1990, pp. 300-307, 1990, IEEE Computer Society, 0-8186-2046-3. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
31 | Philipp W. Besslich |
Heuristic Minimization of MVL Functions: A Direct Cover Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(2), pp. 134-144, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
28 | Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko |
Experiments on FPRM Expressions for Partially Symmetric Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 141-146, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fixed polarity Reed-Muller expression, symmetric functions, MVL functions |
28 | Mostafa I. H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic |
Synthesis of Multivalued Multithreshold Functions for CCD Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(2), pp. 124-133, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
CCD realization of MVL functions, function synthesis, multithreshold functions, multivalued logic, function decomposition, charge- coupled devices |
19 | K. J. Adams, Jonathan G. Campbell, Liam P. Maguire, J. A. C. Webb |
State Assignment Techniques in Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 220-225, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Multiple-Valued Logic, Galois Fields, State Assignment, Transform matrix |
19 | Grant Pogosyan, Akihiro Nozaki |
Join-Irreducible Clones of Multiple-Valued Logic Algebra. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 25th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings, pp. 194-199, 1995, IEEE Computer Society, 0-8186-7118-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
join-irreducible clones, multiple valued logic algebra, synthetic means, lattice elements, join irreducible elements, unary functions, constructive criteria, graph theoretical property, one variable function, k valued logic, graph theory, set theory, multivalued logic, group theory, monoids, join operation, generating system |
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