Search results for "MVL-functions"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
110	Vlad P. Shmerko, Svetlana N. Yanushkevich, Vitaly G. Levashenko, I. Bondar	Technique of Computing Logic Derivatives for MVL-Functions.	ISMVL	1996	DBLP DOI BibTeX RDF	logic derivatives, partial direct, inverse derivatives, matrix approach, MVL switching circuit, truth vectors, multivalued logic, logic processing, MVL-functions
96	Zheng Tang, Okihiko Ishizuka, Koichi Tanno	Learning Multiple-Valued Logic Networks Based on Back Propagation.	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued logic networks learning, canonical realization, initial parameters, neural nets, simulation results, backpropagation, backpropagation, multivalued logic, parameter space, functional completeness
84	Hui Min Wang, Chung-Len Lee 0001, Jwu E. Chen	Factorization of Multi-Valued Logic Functions.	ISMVL	1995	DBLP DOI BibTeX RDF	multi-valued logic function factorization, multi valued logic functions, rectangular covering problem, MVL algebraic factorization algorithm, MVL Boolean properties, purely algebraic factorization algorithm, multilevel implementation, Boolean method, MVL example functions, computational complexity, complexity, Boolean functions, multivalued logic
83	Arkadij Zakrevskij, Lev Zakrevski	Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions.	ISMVL	1997	DBLP DOI BibTeX RDF
78	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan, G. A. Hamid	On the Synthesis of MVL Functions Using Input and Output Phase Assignments.	ISMVL	1997	DBLP DOI BibTeX RDF	MVL functions synthesis, phase assignments, decomposition based mapping, input matrix, output matrix, matching-count matrix, output function number, maximum matching count, switching operations, switching operators, r-valued functions, logic synthesis, minimization, multivalued logic
75	Christian Lang 0001, Bernd Steinbach	Bi-Decomposition of Function Sets in Multiple-Valued Logic for Circuit Design and Data Mining.	Artif. Intell. Rev.	2003	DBLP DOI BibTeX RDF	bi-decomposition, differential calculus, multi-level circuit design, data mining, machine learning, logic synthesis, multiple-valued logic
67	Mitchell A. Thornton	Spectral Transforms of Mixed-radix MVL Functions.	ISMVL	2003	DBLP DOI BibTeX RDF
66	Mostafa I. H. Abd-El-Barr, Bambang A. B. Sarif	Weighted and Ordered Direct Cover Algorithms for Minimization of MVL Functions.	ISMVL	2007	DBLP DOI BibTeX RDF
59	Craig M. Files, Rolf Drechsler, Marek A. Perkowski	Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams.	ISMVL	1997	DBLP DOI BibTeX RDF	learning samples, minterms, machine learning, learning (artificial intelligence), minimization, functional decomposition, multi-valued logic, multi-valued decision diagrams, problem complexity, MVL functions
59	Mostafa I. H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky	Algorithmic Synthesis of MVL Functions for CCD Implementation.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	algorithmic synthesis, CCD implementation, sum of products, logic design, many-valued logics, logic circuits, charge-coupled devices, MVL functions, literals
52	Svetlana N. Yanushkevich, Denis V. Popel, Vlad P. Shmerko, V. Cheushev, Radomir S. Stankovic	Information Theoretic Approach to Minimization of Polynomial Expressions over GF(4).	ISMVL	2000	DBLP DOI BibTeX RDF	multiple-valued logic functions, information theory measures, decision trees, minimization
52	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
35	Ugur Kalay, Marek A. Perkowski, Douglas V. Hall	Highly Testable Boolean Ring Logic Circuits.	ISMVL	1999	DBLP DOI BibTeX RDF	Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits
35	Zeljko Zilic, Zvonko G. Vranesic	New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms.	ISMVL	1996	DBLP DOI BibTeX RDF
35	A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm.	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
33	Anna M. Tomaszewska, Svetlana N. Yanushkevich, Vlad P. Shmerko	The Word-Level Models for Efficient Computation of Multiple-Valued Functions. PART 2: LWL Based Model.	ISMVL	2002	DBLP DOI BibTeX RDF	multiple-valued logic circuits, word-level decision diagrams
33	Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic	Generic Implementation of DD Packages in MVL.	EUROMICRO	1999	DBLP DOI BibTeX RDF
33	Gregory E. Beers, Lizy Kurian John	Novel Memory Bus Driver/Receiver Architecture for Higher Throughput.	VLSI Design	1998	DBLP DOI BibTeX RDF
31	Bambang A. B. Sarif, Mostafa I. H. Abd-El-Barr	The Use of Multiple Connected Pseudo Minterms in the Synthesis of MVL Functions.	ISMVL	2009	DBLP DOI BibTeX RDF
31	Mitchell A. Thornton	The Karhunen-Loève Transform of Discrete MVL Functions.	ISMVL	2005	DBLP DOI BibTeX RDF
31	Mostafa I. H. Abd-El-Barr, H. Choy	Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL Functions.	ISMVL	1992	DBLP DOI BibTeX RDF
31	Mostafa I. H. Abd-El-Barr, M. I. Mahroos	On the Synthesis of MVL Functions for Current-Mode CMOS Circuits Implementation.	ISMVL	1992	DBLP DOI BibTeX RDF
31	Safwat G. Zaky, Zvonko G. Vranesic, Mostafa I. H. Abd-El-Barr	Step-Wise Synthesis of CCD MVL Functions.	ISMVL	1990	DBLP DOI BibTeX RDF
31	Philipp W. Besslich	Heuristic Minimization of MVL Functions: A Direct Cover Approach.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF
28	Svetlana N. Yanushkevich, Jon T. Butler, Gerhard W. Dueck, Vlad P. Shmerko	Experiments on FPRM Expressions for Partially Symmetric Logic Functions.	ISMVL	2000	DBLP DOI BibTeX RDF	fixed polarity Reed-Muller expression, symmetric functions, MVL functions
28	Mostafa I. H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic	Synthesis of Multivalued Multithreshold Functions for CCD Implementation.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	CCD realization of MVL functions, function synthesis, multithreshold functions, multivalued logic, function decomposition, charge- coupled devices
19	K. J. Adams, Jonathan G. Campbell, Liam P. Maguire, J. A. C. Webb	State Assignment Techniques in Multiple-Valued Logic.	ISMVL	1999	DBLP DOI BibTeX RDF	Multiple-Valued Logic, Galois Fields, State Assignment, Transform matrix
19	Grant Pogosyan, Akihiro Nozaki	Join-Irreducible Clones of Multiple-Valued Logic Algebra.	ISMVL	1995	DBLP DOI BibTeX RDF	join-irreducible clones, multiple valued logic algebra, synthetic means, lattice elements, join irreducible elements, unary functions, constructive criteria, graph theoretical property, one variable function, k valued logic, graph theory, set theory, multivalued logic, group theory, monoids, join operation, generating system