Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
128 | Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi |
Read-out schemes for a CNTFET-based crossbar memory. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
carbon nanotube field effect transistor, crossbar design, read-out circuit, noise margin |
109 | Hamidreza Hashempour, Fabrizio Lombardi |
Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
CNTFET, fault detection, nanotechnology, carbon nanotube, defect modeling, CNT |
82 | Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin |
Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design. |
NanoNet |
2009 |
DBLP DOI BibTeX RDF |
Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling |
59 | Dinh Sy Hien |
Development of Quantum Device Simulator, NEMO-VN2. |
DELTA |
2010 |
DBLP DOI BibTeX RDF |
quantum device simulator, phonon scattering, planar CNTFET, coaxial CNTFET |
48 | Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot |
Novel CNTFET-based Reconfigurable Logic Gate Design. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Gopalakrishnan Sundararajan, Chris Winstead |
CNTFET-RFB: An Error Correction Implementation for Multi-valued CNTFET Logic. |
ISMVL |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad, Seyed Erfan Fatemieh |
New design for error-resilient approximate multipliers used in image processing in CNTFET technology. |
J. Supercomput. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Rabe'e Sharifi Rad, Mokhtar Mohammadi Ghanatghestani, Malihe Hashemipour |
Efficient ATFA design based on CNTFET technology for error-tolerant applications. |
Circuits Syst. Signal Process. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Pegah Foroutan, Keivan Navi |
A Novel Current Mode Approximate Multiplier Scheme Based on 4:2 and 5:2 Compressors with Low Power Consumption and High Speed in CNTFET Technology. |
Circuits Syst. Signal Process. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta |
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications. |
Circuits Syst. Signal Process. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Aiman Malik, Md. Shahbaz Hussain, Mohd. Hasan |
Energy-Efficient Exact and Approximate CNTFET-Based Ternary Full Adders. |
Circuits Syst. Signal Process. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Zhongzhen Tong, Yilin Xu, Yunlong Liu, Xinrui Duan, Hao Tang, Suteng Zhao, Chenghang Li, Zhiting Lin, Xiulong Wu, Zhaohao Wang, Xiaoyang Lin |
A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Tabassum Khurshid, Vikram Singh 0006 |
CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits. |
J. Circuits Syst. Comput. |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri |
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures. |
IEEE Embed. Syst. Lett. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Milad Tanavardi Nasab, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari |
High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator. |
IEEE Trans. Emerg. Top. Comput. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Anisha Paul, Buddhadev Pradhan |
Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator. |
Circuits Syst. Signal Process. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, G. Saravanan, S. Jayanthi, P. Raja, Kulbhushan Sharma, S. Nireshkumar |
High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications. |
J. Circuits Syst. Comput. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Sharvani Gadgil, Goli Naga Sandesh, Chetan Vudadha |
Power efficient designs of CNTFET-based ternary SRAM. |
Microelectron. J. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Muhammad I. Masud, Iqbal A. Khan |
CNTFET Based Fully Differential First Order All Pass Filter. |
Comput. Syst. Sci. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Rawan Mohammed, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
CNTFET-based Approximate Ternary Adder Design. |
ICECS |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Amandeep Singh Rehal |
Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology. |
NANOARCH |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Priya Singh, Uma Sharma |
Exploring Low-Power Implementation Techniques for 2:1 MUX Using Conventional and CNTFET Technology: a Performance Comparison. |
ICCCNT |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari |
Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons. |
IEEE Trans. Emerg. Top. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Salimeh Shahrabadi |
Challenges and solutions of working under threshold supply-voltage, for CNTFET-based SRAM-bitcell. |
IET Circuits Devices Syst. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Vikash Prasad, Debaprasad Das |
Design of Voltage Level Shifter Using CNTFET and Analysis of Process Voltage Temperature Variation. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | A. Bernard Rayappa, T. V. P. Sundararajan |
Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Vijay Kumar Sharma |
CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Yogesh Shrivastava, Tarun Kumar Gupta |
Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, M. Muthukrishnan |
Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology. |
J. Circuits Syst. Comput. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Rawan Mohammed, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, Ahmed G. Radwan |
CNTFET-based ternary address decoder design. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee, Maryam Bigonah |
SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits. |
Int. J. Circuit Theory Appl. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury |
Design of novel 3T ternary DRAM with single word-line using CNTFET. |
Microelectron. J. |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
CNTFET quaternary multipliers are less efficient than the corresponding binary ones. |
CoRR |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Bharathi Raj Muthu, Ewins Pon Pushpa, Vaithiyanathan Dhandapani, Kamala Jayaraman, Hemalatha Vasanthakumar, Won-Chun Oh, Suresh Sagadevan |
Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Suvarna Mujumdar, Sajad A. Loan, Nelofer Afzal |
CNTFET based 2-bit Unary weighted Current Steering Digital to Analog Converter using Cascode Current Mirror Technique. |
ICM |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Steven Bos, Halvor Nybø Risto, Henning Gundersen |
Beyond CMOS: Ternary and mixed radix CNTFET circuit design, simulation and verification. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Sarada Musala, Aswini Valluri, P. Gurubrahmam, G. Meghana, N. Yashoda |
Design of CNTFET based Ternary Subtractor using Unary Operators. |
iSES |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Siddharth T, Sharvani Gadgil, Chetan Vudadha |
Design of CNTFET-based Ternary Logic circuits using Low power Encoder. |
iSES |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Alexander C. Bodoh, Ashiq A. Sakib |
Comparative Analysis of CNTFET and CMOS based NCL Asynchronous Circuits: A Study of Scaling Trends. |
UEMCON |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Hossein Moaiyeri, Mohammad Khaleqi Qaleh Jooq, Alaaddin Al-Shidaifat, Hanjung Song |
Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
22 | A. Gangadhar, K. Babulu |
Design of low-power and high-speed CNTFET-based TCAM cell for future generation networks. |
J. Supercomput. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Muhammad I. Masud, Abu Khari bin A'Ain, Iqbal A. Khan, Nasir Shaikh-Husin |
CNTFET based Voltage Mode MISO Active only Biquadratic Filter for Multi-GHz Frequency Applications. |
Circuits Syst. Signal Process. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan |
A Novel Darlington-Based 8T CNTFET SRAM Cell for Low Power Applications. |
J. Circuits Syst. Comput. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Khaleqi Qaleh Jooq, Ali Bozorgmehr, Sattar Mirzakuchaki |
A low-power delay stage ring VCO based on wrap-gate CNTFET technology for X-band satellite communication applications. |
Int. J. Circuit Theory Appl. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Amr Mohammaden, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, Ahmed G. Radwan |
CNTFET design of a multiple-port ternary register file. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Islombek Mamatov, Yasin Özçelep, Firat Kaçar |
Voltage differencing buffered amplifier based low power, high frequency and universal filters using 32 nm CNTFET technology. |
Microelectron. J. |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
Best CNTFET Ternary Adders? |
CoRR |
2021 |
DBLP BibTeX RDF |
|
22 | Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury |
Design of Novel 3T Ternary DRAM with Single Word-Line using CNTFET. |
CoRR |
2021 |
DBLP BibTeX RDF |
|
22 | Suvarna Mujumdar, Nelofer Afzal, Sajad A. Loan |
A 4-bit Binary weighted Current Steering Digital To Analog Converter based on CNTFET. |
ICM |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Boli Peng, Sven Mothes, Manojkumar Annamalai, Michael Schröter |
Evaluation of Stacked-CNTFET Structures for High-performance Applications. |
BCICTS |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Takshashila Pathade, Yash Agrawal, Rutu Parekh, Girish Kumar Mekala |
CNTFET Based Low Power Repeaters for On-Chip Interconnect System. |
VDAT |
2021 |
DBLP DOI BibTeX RDF |
|
22 | K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi |
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. |
VDAT |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Khaleqi Qaleh Jooq, Ali Mir 0001, Sattar Mirzakuchaki, Ali Farmani |
Design and performance analysis of wrap-gate CNTFET-based ring oscillators for IoT applications. |
Integr. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Arezoo Dabaghi Zarandi, Mohammad Reza Reshadinezhad, Antonio Rubio 0001 |
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells. |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Trapti Sharma, Laxmi Kumre |
Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology. |
Circuits Syst. Signal Process. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Trapti Sharma, Laxmi Kumre |
Design of low power multi-ternary digit multiplier in CNTFET technology. |
Microprocess. Microsystems |
2020 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, K. Gunavathi |
High Stable and Low Power 8T CNTFET SRAM Cell. |
J. Circuits Syst. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Maryam Shahangian, Seied Ali Hosseini, Reza Faghih Mirzaee |
A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET. |
J. Circuits Syst. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, K. Gunavathi |
High Stable and Low Power 10T CNTFET SRAM Cell. |
J. Circuits Syst. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Mohd Yasir, Naushad Alam |
Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications. |
J. Circuits Syst. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Khaleqi Qaleh Jooq, Ali Bozorgmehr, Sattar Mirzakuchaki |
A low power and energy efficient 4: 2 precise compressor based on novel 14T hybrid full adders in 10 nm wrap gate CNTFET technology. |
Microelectron. J. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | A. Arulmary, V. Rajamani, T. Kavitha |
Study of uniformly doped nano scale single-walled CNTFET under dark and illuminated conditions. |
Microelectron. J. |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Amr Mohammaden, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
Memristor-CNTFET based Ternary Full Adders. |
MWSCAS |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Ramzi A. Jaber, Ali M. Haidar 0001, Abdallah Kassem |
CNTFET-Based Design of Ternary Multiplier using Only Multiplexers. |
ICM |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Doaa K. Abdelrahman, Rawan Mohammed, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
Comparative Study of CNTFET Implementations of 1-trit Multiplier. |
ICM |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Ashiq A. Sakib, Scott C. Smith |
Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology. |
ICECS |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Annapurna Raina, Shirin Dewan, Reena Monica P |
ENERGY EFFICIENT DIGITAL CIRCUITS Using HYBRID MTJ and CNTFET. |
iSES |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali |
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits. |
IEEE Trans. Very Large Scale Integr. Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Ajay Kumar Dadoria, Kavita Khare |
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology. |
Circuits Syst. Signal Process. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Trapti Sharma, Laxmi Kumre |
CNTFET-Based Design of Ternary Arithmetic Modules. |
Circuits Syst. Signal Process. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Sandeep Garg, Tarun Kumar Gupta |
Low leakage domino logic circuit for wide fan-in gates using CNTFET. |
IET Circuits Devices Syst. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | V. M. Senthilkumar, S. Ravindrakumar, D. Nithya, N. V. Kousik |
A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing. |
Microprocess. Microsystems |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Morteza Dadashi Gavaber, Mehrdad Poorhosseini, Saadat Pourmozafari |
Novel Architecture for Low-Power CNTFET-Based Compressors. |
J. Circuits Syst. Comput. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj |
A low leakage TG-CNTFET-based inexact full adder for low power image processing applications. |
Int. J. Circuit Theory Appl. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Mukesh Kumar, Jagpal Singh Ubhi |
Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale. |
Int. J. Circuit Theory Appl. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Sayed Mohammad Ali Zanjani, Massoud Dousti, Mehdi Dolatshahi |
A new low-power, universal, multi-mode Gm-C filter in CNTFET technology. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta |
Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM. |
Microelectron. J. |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Arushi Shrivastava, Parul Damahe, Vijay Rao Kumbhare, Manoj Kumar Majumder |
Designing SRAM Using CMOS and CNTFET at 32 nm Technology. |
iSES |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Narges Hajizadeh Bastani, Mohammad Hossein Moaiyeri, Keivan Navi |
An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic. |
Circuits Syst. Signal Process. |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Sayed Mohammad Ali Zanjani, Massoud Dousti, Mehdi Dolatshahi |
Inverter-based, low-power and low-voltage, new mixed-mode Gm-C filter in subthreshold CNTFET technology. |
IET Circuits Devices Syst. |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Nancy S. Soliman, Mohammed E. Fouda, Ahmed G. Radwan |
Memristor-CNTFET based ternary logic gates. |
Microelectron. J. |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Ebrahim Abiri, Abdolreza Darabi |
CNTFET-based divide-by-N/[N+1] DMFPs using m-GDI method for future generation communication networks. |
Nano Commun. Networks |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Mahmood Uddin Mohammed, Rakesh Vijjapuram, Masud H. Chowdhury |
Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate. |
MWSCAS |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Nancy S. Soliman, Mohammed E. Fouda, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan |
Memristor-CNTFET based Ternary Comparator unit. |
ICM |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Subhendu Kumar Sahoo, Krishna Dhoot, Rasmita Sahoo |
High Performance Ternary Multiplier Using CNTFET. |
ISVLSI |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Zahra Zareei, Seyedeh Mohtaram Daryabari |
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
22 | T. R. Rajalakshmi, R. Sudhakar 0001 |
Impact of Single Event Upset on Voltage and Current Behaviors of CNTFET SRAM and a Comparison with CMOS SRAM. |
J. Circuits Syst. Comput. |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Asma Torkzadeh Mahani, Peiman Keshavarzian |
A novel energy-efficient and high speed full adder using CNTFET. |
Microelectron. J. |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Xuan Hu, Joseph S. Friedman |
Transient model with interchangeability for dual-gate ambipolar CNTFET logic design. |
NANOARCH |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Xuan Hu, Joseph S. Friedman |
Closed-form model for dual-gate ambipolar CNTFET circuit design. |
ISCAS |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo |
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET. |
iNIS |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Geunho Cho, Fabrizio Lombardi |
Design and process variation analysis of CNTFET-based ternary memory cells. |
Integr. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Mona Moradi, Reza Faghih Mirzaee, Keivan Navi |
New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters. |
IEICE Trans. Electron. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Maryam Sadat Mastoori, Farhad Razaghian |
A Novel Energy-Efficient Ternary Successor and Predecessor Using CNTFET. |
Circuits Syst. Signal Process. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Fereshteh Jafarzadehpour, Peiman Keshavarzian |
Low-power consumption ternary full adder based on CNTFET. |
IET Circuits Devices Syst. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad, Ali Bohlooli, Mahyar Shahsavari |
Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. |
Microelectron. J. |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Bodapati Srinivasu, K. Sridharan 0001 |
Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology. |
IEEE Trans. Circuits Syst. II Express Briefs |
2016 |
DBLP DOI BibTeX RDF |
|