Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
128 | Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi |
Read-out schemes for a CNTFET-based crossbar memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 167-170, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
carbon nanotube field effect transistor, crossbar design, read-out circuit, noise margin |
109 | Hamidreza Hashempour, Fabrizio Lombardi |
Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 841-846, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
CNTFET, fault detection, nanotechnology, carbon nanotube, defect modeling, CNT |
82 | Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin |
Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NanoNet ![In: Nano-Net - 4th International ICST Conference, Nano-Net 2009, Lucerne, Switzerland, October 18-20, 2009. Proceedings, pp. 105-110, 2009, Springer, 978-3-642-04849-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling |
59 | Dinh Sy Hien |
Development of Quantum Device Simulator, NEMO-VN2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 170-173, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
quantum device simulator, phonon scattering, planar CNTFET, coaxial CNTFET |
48 | Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot |
Novel CNTFET-based Reconfigurable Logic Gate Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 276-277, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
43 | Gopalakrishnan Sundararajan, Chris Winstead |
CNTFET-RFB: An Error Correction Implementation for Multi-valued CNTFET Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 46th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2016, Sapporo, Japan, May 18-20, 2016, pp. 11-16, 2016, IEEE Computer Society, 978-1-4673-9489-5. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Samira Shirinabadi Farahani, Mohammad Reza Reshadinezhad, Seyed Erfan Fatemieh |
New design for error-resilient approximate multipliers used in image processing in CNTFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 80(3), pp. 3694-3712, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Rabe'e Sharifi Rad, Mokhtar Mohammadi Ghanatghestani, Malihe Hashemipour |
Efficient ATFA design based on CNTFET technology for error-tolerant applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 43(2), pp. 1119-1143, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Pegah Foroutan, Keivan Navi |
A Novel Current Mode Approximate Multiplier Scheme Based on 4:2 and 5:2 Compressors with Low Power Consumption and High Speed in CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 43(5), pp. 3042-3072, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, Kulbhushan Sharma, Ashish Sachdeva, Lipika Gupta |
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 43(3), pp. 1627-1660, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Aiman Malik, Md. Shahbaz Hussain, Mohd. Hasan |
Energy-Efficient Exact and Approximate CNTFET-Based Ternary Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 43(5), pp. 2982-3003, May 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Zhongzhen Tong, Yilin Xu, Yunlong Liu, Xinrui Duan, Hao Tang, Suteng Zhao, Chenghang Li, Zhiting Lin, Xiulong Wu, Zhaohao Wang, Xiaoyang Lin |
A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 71(2), pp. 606-619, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Tabassum Khurshid, Vikram Singh 0006 |
CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 33(5), pp. 2450085:1-2450085:24, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
22 | Ayoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri |
High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 15(1), pp. 33-36, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Milad Tanavardi Nasab, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari |
High-Performance and Robust Spintronic/CNTFET-Based Binarized Neural Network Hardware Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 11(2), pp. 527-533, April - June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Anisha Paul, Buddhadev Pradhan |
Design of CNTFET-Based Ternary and Quaternary Magnitude Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(9), pp. 5634-5662, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, G. Saravanan, S. Jayanthi, P. Raja, Kulbhushan Sharma, S. Nireshkumar |
High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 32(17), pp. 2350291:1-2350291:23, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Sharvani Gadgil, Goli Naga Sandesh, Chetan Vudadha |
Power efficient designs of CNTFET-based ternary SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 139, pp. 105884, September 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Muhammad I. Masud, Iqbal A. Khan |
CNTFET Based Fully Differential First Order All Pass Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Syst. Sci. Eng. ![In: Comput. Syst. Sci. Eng. 44(3), pp. 2425-2438, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Rawan Mohammed, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
CNTFET-based Approximate Ternary Adder Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, pp. 1-4, 2023, IEEE, 979-8-3503-2649-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Amandeep Singh Rehal |
Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, NANOARCH 2023, Dresden, Germany, December 18-20, 2023, pp. 1:1-1:5, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Priya Singh, Uma Sharma |
Exploring Low-Power Implementation Techniques for 2:1 MUX Using Conventional and CNTFET Technology: a Performance Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari |
Nonvolatile Associative Memory Design Based on Spintronic Synapses and CNTFET Neurons. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 10(1), pp. 428-437, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Salimeh Shahrabadi |
Challenges and solutions of working under threshold supply-voltage, for CNTFET-based SRAM-bitcell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 16(8), pp. 569-580, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Vikash Prasad, Debaprasad Das |
Design of Voltage Level Shifter Using CNTFET and Analysis of Process Voltage Temperature Variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(10), pp. 2250185:1-2250185:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | A. Bernard Rayappa, T. V. P. Sundararajan |
Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(5), pp. 2250080:1-2250080:24, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Vijay Kumar Sharma |
CNTFET Circuit-Based Wide Fan-In Domino Logic for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(2), pp. 2250036:1-2250036:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Yogesh Shrivastava, Tarun Kumar Gupta |
Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(5), pp. 2250082:1-2250082:16, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, M. Muthukrishnan |
Design of High Stability and Low Power 7T SRAM Cell in 32-NM CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(13), pp. 2250233:1-2250233:23, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Rawan Mohammed, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, Ahmed G. Radwan |
CNTFET-based ternary address decoder design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(10), pp. 3682-3691, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Nabiollah Shiri, Ayoub Sadeghi, Mahmood Rafiee, Maryam Bigonah |
SR-GDI CNTFET-based magnitude comparator for new generation of programmable integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 50(5), pp. 1511-1536, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury |
Design of novel 3T ternary DRAM with single word-line using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 126, pp. 105498, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
Two New CNTFET Quaternary Full Adders for Carry-Propagate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.01401, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
Ternary and Quaternary CNTFET Full Adders are less efficient than the Binary Ones for Carry-Propagate Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2207.04839, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
CNTFET quaternary multipliers are less efficient than the corresponding binary ones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2206.03252, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Bharathi Raj Muthu, Ewins Pon Pushpa, Vaithiyanathan Dhandapani, Kamala Jayaraman, Hemalatha Vasanthakumar, Won-Chun Oh, Suresh Sagadevan |
Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sensors ![In: Sensors 22(1), pp. 33, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Suvarna Mujumdar, Sajad A. Loan, Nelofer Afzal |
CNTFET based 2-bit Unary weighted Current Steering Digital to Analog Converter using Cascode Current Mirror Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2022, Casablanca, Morocco, December 4-7, 2022, pp. 70-73, 2022, IEEE, 978-1-6654-9324-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Steven Bos, Halvor Nybø Risto, Henning Gundersen |
Beyond CMOS: Ternary and mixed radix CNTFET circuit design, simulation and verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 80-85, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Sarada Musala, Aswini Valluri, P. Gurubrahmam, G. Meghana, N. Yashoda |
Design of CNTFET based Ternary Subtractor using Unary Operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022, pp. 378-383, 2022, IEEE, 979-8-3503-9922-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Siddharth T, Sharvani Gadgil, Chetan Vudadha |
Design of CNTFET-based Ternary Logic circuits using Low power Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2022, Warangal, India, December 18-22, 2022, pp. 142-147, 2022, IEEE, 979-8-3503-9922-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Alexander C. Bodoh, Ashiq A. Sakib |
Comparative Analysis of CNTFET and CMOS based NCL Asynchronous Circuits: A Study of Scaling Trends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UEMCON ![In: 13th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, UEMCON 2022, New York, NY, USA, October 26-29, 2022, pp. 407-412, 2022, IEEE, 978-1-6654-9299-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Hossein Moaiyeri, Mohammad Khaleqi Qaleh Jooq, Alaaddin Al-Shidaifat, Hanjung Song |
Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 132641-132651, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | A. Gangadhar, K. Babulu |
Design of low-power and high-speed CNTFET-based TCAM cell for future generation networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 77(9), pp. 10012-10022, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Muhammad I. Masud, Abu Khari bin A'Ain, Iqbal A. Khan, Nasir Shaikh-Husin |
CNTFET based Voltage Mode MISO Active only Biquadratic Filter for Multi-GHz Frequency Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(10), pp. 4721-4740, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan |
A Novel Darlington-Based 8T CNTFET SRAM Cell for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(12), pp. 2150213:1-2150213:17, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Khaleqi Qaleh Jooq, Ali Bozorgmehr, Sattar Mirzakuchaki |
A low-power delay stage ring VCO based on wrap-gate CNTFET technology for X-band satellite communication applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 49(1), pp. 142-158, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 111, pp. 105033, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Amr Mohammaden, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, Ahmed G. Radwan |
CNTFET design of a multiple-port ternary register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 113, pp. 105076, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Islombek Mamatov, Yasin Özçelep, Firat Kaçar |
Voltage differencing buffered amplifier based low power, high frequency and universal filters using 32 nm CNTFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 107, pp. 104948, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Etiemble |
Best CNTFET Ternary Adders? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2101.01516, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
22 | Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury |
Design of Novel 3T Ternary DRAM with Single Word-Line using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2108.09342, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
22 | Suvarna Mujumdar, Nelofer Afzal, Sajad A. Loan |
A 4-bit Binary weighted Current Steering Digital To Analog Converter based on CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: International Conference on Microelectronics, ICM 2021, New Cairo City, Egypt, December 19-22, 2021, pp. 157-160, 2021, IEEE, 978-1-6654-0839-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Boli Peng, Sven Mothes, Manojkumar Annamalai, Michael Schröter |
Evaluation of Stacked-CNTFET Structures for High-performance Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BCICTS ![In: IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2021, Monterey, CA, USA, December 5-8, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3990-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Takshashila Pathade, Yash Agrawal, Rutu Parekh, Girish Kumar Mekala |
CNTFET Based Low Power Repeaters for On-Chip Interconnect System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | K. Lakshmi BhanuPrakash Reddy, K. B. Dheeraj Kumar, Vikramkumar Pudi |
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-1992-5. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Khaleqi Qaleh Jooq, Ali Mir 0001, Sattar Mirzakuchaki, Ali Farmani |
Design and performance analysis of wrap-gate CNTFET-based ring oscillators for IoT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 70, pp. 116-125, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Arezoo Dabaghi Zarandi, Mohammad Reza Reshadinezhad, Antonio Rubio 0001 |
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 58585-58593, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Trapti Sharma, Laxmi Kumre |
Energy-Efficient Ternary Arithmetic Logic Unit Design in CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 39(7), pp. 3265-3288, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Trapti Sharma, Laxmi Kumre |
Design of low power multi-ternary digit multiplier in CNTFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 73, pp. 102959, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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22 | M. Elangovan, K. Gunavathi |
High Stable and Low Power 8T CNTFET SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(5), pp. 2050080:1-2050080:18, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Maryam Shahangian, Seied Ali Hosseini, Reza Faghih Mirzaee |
A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(12), pp. 2050196:1-2050196:23, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | M. Elangovan, K. Gunavathi |
High Stable and Low Power 10T CNTFET SRAM Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(10), pp. 2050158:1-2050158:19, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Mohd Yasir, Naushad Alam |
Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 29(9), pp. 2050143:1-2050143:20, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Khaleqi Qaleh Jooq, Ali Bozorgmehr, Sattar Mirzakuchaki |
A low power and energy efficient 4: 2 precise compressor based on novel 14T hybrid full adders in 10 nm wrap gate CNTFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 104, pp. 104892, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | A. Arulmary, V. Rajamani, T. Kavitha |
Study of uniformly doped nano scale single-walled CNTFET under dark and illuminated conditions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 104, pp. 104889, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Amr Mohammaden, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
Memristor-CNTFET based Ternary Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020, pp. 562-565, 2020, IEEE, 978-1-7281-8058-8. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Ramzi A. Jaber, Ali M. Haidar 0001, Abdallah Kassem |
CNTFET-Based Design of Ternary Multiplier using Only Multiplexers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 32nd International Conference on Microelectronics, ICM 2020, Aqaba, Jordan, December 14-17, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9664-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Doaa K. Abdelrahman, Rawan Mohammed, Mohammed E. Fouda, Lobna A. Said, Ahmed G. Radwan |
Comparative Study of CNTFET Implementations of 1-trit Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 32nd International Conference on Microelectronics, ICM 2020, Aqaba, Jordan, December 14-17, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9664-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Ashiq A. Sakib, Scott C. Smith |
Implementation of Static NCL Threshold Gates Using Emerging CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020, Glasgow, Scotland, UK, November 23-25, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-6044-3. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Annapurna Raina, Shirin Dewan, Reena Monica P |
ENERGY EFFICIENT DIGITAL CIRCUITS Using HYBRID MTJ and CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2020 (Formerly iNiS), Chennai, India, December 14-16, 2020, pp. 127-132, 2020, IEEE, 978-1-6654-0478-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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22 | Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali |
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(1), pp. 37-46, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Ajay Kumar Dadoria, Kavita Khare |
Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 38(9), pp. 4338-4356, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Trapti Sharma, Laxmi Kumre |
CNTFET-Based Design of Ternary Arithmetic Modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 38(10), pp. 4640-4666, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Sandeep Garg, Tarun Kumar Gupta |
Low leakage domino logic circuit for wide fan-in gates using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(2), pp. 163-173, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | V. M. Senthilkumar, S. Ravindrakumar, D. Nithya, N. V. Kousik |
A vedic mathematics based processor core for discrete wavelet transform using FinFET and CNTFET technology for biomedical signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 71, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Morteza Dadashi Gavaber, Mehrdad Poorhosseini, Saadat Pourmozafari |
Novel Architecture for Low-Power CNTFET-Based Compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 28(12), pp. 1950207:1-1950207:16, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Candy Goyal, Jagpal Singh Ubhi, Balwinder Raj |
A low leakage TG-CNTFET-based inexact full adder for low power image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 47(9), pp. 1446-1458, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Mukesh Kumar, Jagpal Singh Ubhi |
Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 47(11), pp. 1775-1785, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Sayed Mohammad Ali Zanjani, Massoud Dousti, Mehdi Dolatshahi |
A new low-power, universal, multi-mode Gm-C filter in CNTFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 90, pp. 342-352, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Pramod Kumar Patel, M. M. Malik, Tarun Kumar Gupta |
Performance evaluation of single-ended disturb-free CNTFET-based multi-Vt SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 90, pp. 19-28, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Arushi Shrivastava, Parul Damahe, Vijay Rao Kumbhare, Manoj Kumar Majumder |
Designing SRAM Using CMOS and CNTFET at 32 nm Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2019 (Formerly iNiS), Rourkela, India, December 16-18, 2019, pp. 284-287, 2019, IEEE, 978-1-7281-4655-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Narges Hajizadeh Bastani, Mohammad Hossein Moaiyeri, Keivan Navi |
An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 37(5), pp. 1863-1883, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Sayed Mohammad Ali Zanjani, Massoud Dousti, Mehdi Dolatshahi |
Inverter-based, low-power and low-voltage, new mixed-mode Gm-C filter in subthreshold CNTFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 12(6), pp. 681-688, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Nancy S. Soliman, Mohammed E. Fouda, Ahmed G. Radwan |
Memristor-CNTFET based ternary logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 72, pp. 74-85, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Ebrahim Abiri, Abdolreza Darabi |
CNTFET-based divide-by-N/[N+1] DMFPs using m-GDI method for future generation communication networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Nano Commun. Networks ![In: Nano Commun. Networks 18, pp. 1-16, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Mahmood Uddin Mohammed, Rakesh Vijjapuram, Masud H. Chowdhury |
Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018, Windsor, ON, Canada, August 5-8, 2018, pp. 1106-1109, 2018, IEEE, 978-1-5386-7392-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Nancy S. Soliman, Mohammed E. Fouda, Lobna A. Said, Ahmed H. Madian, Ahmed G. Radwan |
Memristor-CNTFET based Ternary Comparator unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 30th International Conference on Microelectronics, ICM 2018, Sousse, Tunisia, December 16-19, 2018, pp. 148-151, 2018, IEEE, 978-1-5386-8167-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Subhendu Kumar Sahoo, Krishna Dhoot, Rasmita Sahoo |
High Performance Ternary Multiplier Using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 269-274, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Zahra Zareei, Seyedeh Mohtaram Daryabari |
A Novel High-Speed, Low-Power CNTFET-Based Inexact Full Adder Cell for Image Processing Application of Motion Detector. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(5), pp. 1750082:1-1750082:15, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | T. R. Rajalakshmi, R. Sudhakar 0001 |
Impact of Single Event Upset on Voltage and Current Behaviors of CNTFET SRAM and a Comparison with CMOS SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 26(2), pp. 1750020:1-1750020:14, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Asma Torkzadeh Mahani, Peiman Keshavarzian |
A novel energy-efficient and high speed full adder using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 61, pp. 79-88, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Xuan Hu, Joseph S. Friedman |
Transient model with interchangeability for dual-gate ambipolar CNTFET logic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017, pp. 61-66, 2017, IEEE, 978-1-5090-6037-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Xuan Hu, Joseph S. Friedman |
Closed-form model for dual-gate ambipolar CNTFET circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo |
Design of a High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2017, Bhopal, India, December 18-20, 2017, pp. 46-49, 2017, IEEE, 978-1-5386-1356-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Geunho Cho, Fabrizio Lombardi |
Design and process variation analysis of CNTFET-based ternary memory cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 54, pp. 97-108, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Mona Moradi, Reza Faghih Mirzaee, Keivan Navi |
New Current-Mode Multipliers by CNTFET-Based n-Valued Binary Converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 99-C(1), pp. 100-107, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Maryam Sadat Mastoori, Farhad Razaghian |
A Novel Energy-Efficient Ternary Successor and Predecessor Using CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 35(3), pp. 875-895, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Fereshteh Jafarzadehpour, Peiman Keshavarzian |
Low-power consumption ternary full adder based on CNTFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 10(5), pp. 365-374, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad, Ali Bohlooli, Mahyar Shahsavari |
Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 53, pp. 156-166, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Bodapati Srinivasu, K. Sridharan 0001 |
Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 63-II(8), pp. 753-757, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|