|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 19 occurrences of 15 keywords
|
|
|
Results
Found 42 publication records. Showing 42 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
145 | Sohraab Soltani, Hayder Radha |
PEEC: a channel-adaptive feedback-based error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 26(8), pp. 1376-1385, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
107 | Hao Yu 0001, Lei He 0001 |
Vector potential equivalent circuit based on PEEC inversion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 718-723, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
96 | Giulio Antonini, Albert E. Ruehli |
Fast Multipole and Multifunction PEEC Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 2(4), pp. 288-298, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
PEEC method, signal integrity, Modeling techniques |
96 | Giulio Antonini |
Fast Multipole Method for Time Domain PEEC Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Mob. Comput. ![In: IEEE Trans. Mob. Comput. 2(4), pp. 275-287, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
PEEC analysis, Numerical methods, equivalent circuits, Fast Multipole Method |
88 | Dipanjan Gope, Albert E. Ruehli, Vikram Jandhyala |
Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(1), pp. 60-68, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
77 | Hao Yu 0001, Lei He 0001 |
A provably passive and cost-efficient model for inductive interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8), pp. 1283-1294, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Vikram Jandhyala, Yong Wang 0006, Dipanjan Gope, C.-J. Richard Shi |
Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 38-42, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Vinayak Honkote, Baris Taskin |
PEEC based parasitic modeling for power analysis on custom rotary rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 111-116, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
resonant clocking, simulation, modeling, interconnect |
49 | Philippe Artillan, Bruno Estibals, Alain Salles, Jean Abboud, Pierre Aloisi, Corinne Alonso |
A PEEC approach for circular spiral inductive components modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 301-304, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
38 | Sohraab Soltani, Hayder Radha |
Performance evaluation of error control protocols over finite-state Markovian channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: 42nd Annual Conference on Information Sciences and Systems, CISS 2008, Princeton, NJ, USA, 19-21 March 2008, pp. 1131-1136, 2008, IEEE, 978-1-4244-2246-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
30 | Muhammad Adil Khattak, Daniele Romano, Giulio Antonini, Francesco Ferranti |
Efficient Frequency and Time-Domain Simulations of Delayed PEEC Models With Proper Orthogonal Decomposition Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 168-178, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
30 | Bin Zhao, Guanghao Yu, Dong Wang, Lei Chen, Yi An |
Calculation of mutual impedance of ballastless track circuit based on PEEC-Carson method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Simul. Model. Pract. Theory ![In: Simul. Model. Pract. Theory 128, pp. 102796, November 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
30 | Lihong Feng, Luigi Lombardi, Peter Benner, Daniele Romano, Giulio Antonini |
Model Order Reduction for Delayed PEEC Models With Guaranteed Accuracy and Observed Stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(10), pp. 4177-4190, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Yan Li 0081, Lidan Fang, Tuomin Tao, Da Li, En-Xiao Liu, Ning Jin 0001, Manareldeen Ahmed, Erping Li 0001 |
Modeling and Signal Integrity Analysis of RRAM-Based Neuromorphic Chip Crossbar Array Using Partial Equivalent Element Circuit (PEEC) Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 69(9), pp. 3490-3500, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
30 | Saiyd Ahyoune, Javier J. Sieiro, Tomás Carrasco Carrillo, Neus Vidal, José María López-Villegas, Elisenda Roca, Francisco V. Fernández 0001 |
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 63, pp. 332-341, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
30 | Albert E. Ruehli, Giulio Antonini, Lijun Jiang |
Skin-Effect Loss Models for Time- and Frequency-Domain PEEC Solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. IEEE ![In: Proc. IEEE 101(2), pp. 451-472, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Yanchao Sun, Junjun Wang, Xinwei Song, Wen Li |
PEEC Modeling for Linear and Platy Structures with Efficient Capacitance Calculations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIC (2) ![In: Intelligent Computing Theories and Technology - 9th International Conference, ICIC 2013, Nanning, China, July 28-31, 2013. Proceedings, pp. 427-434, 2013, Springer, 978-3-642-39481-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
30 | Y. Zhang, N. H. W. Fong, David C. W. Ng, Ngai Wong |
Co-simulation of RFIC with bondwire antenna via retarded PEEC method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012, pp. 229-232, 2012, IEEE, 978-1-4673-0218-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
30 | Giulio Antonini, Daniele Frigioni, Giuseppe Miscione |
Hybrid Formulation of the Equation Systems of the 3-D PEEC Model Based on Graph Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1), pp. 249-261, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
30 | Min Shi, Boye Annfelt Høverstad |
PEEC: Evolving efficient connections using Pareto optimality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2009, Trondheim, Norway, 18-21 May, 2009, pp. 1578-1584, 2009, IEEE, 978-1-4244-2958-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
30 | Sergey Kochetov, Günter Wollenberg |
Simulation von 3D-Verbindungsstrukturen im Zeitbereich - Stabile Lösungen durch Modifikation der PEEC-Methode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMV ![In: EMV 2006 - Internationale Fachmesse und Kongress für Elektromagnetische Verträglichkeit - 7. bis 9. März 2006, Düsseldorf, pp. 165-172, 2006, VDE-Verlag, 3-8007-2933-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
30 | Qing-Long Han |
Stability analysis for a partial element equivalent circuit (PEEC) model of neutral type. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 33(4), pp. 321-332, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Haitian Hu, Sachin S. Sapatnekar |
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 434-, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
30 | Phillip J. Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos |
Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7), pp. 877-886, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Giulio Antonini |
Fast multipole method based extraction of PEEC parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 509-512, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Liu Yang, Xiaobo Guo, Zeyi Wang |
An efficient method MEGCR for solving systems with multiple right-hand sides in 3-D parasitic inductance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 702-706, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Inductance extraction, Multiple right-hand sides, Multipole method, PEEC |
27 | Tao Lin, Michael W. Beattie, Lawrence T. Pileggi |
On the efficacy of simplified 2D on-chip inductance models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 757-762, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
PEEC, on-chip inductance, sparsified model |
27 | Junfeng Wang 0005, Johannes Tausch, Jacob K. White 0001 |
A wide frequency range surface integral formulation for 3-D RLC extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 453-458, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
FastHenry, PEEC, impedance extraction, surface integral equation, electromagnetics |
27 | Nuno Alexandre Marques, Mattan Kamon, Jacob K. White 0001, Luís Miguel Silveira |
An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 538-543, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Passive Model Order Reduction, Modified Nodal Analysis, PEEC, Extraction, Interconnect Modeling |
19 | Tuck Boon Chan, Hsinchia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen |
LTCC spiral inductor modeling, synthesis, and optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 768-771, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | N. Hassaïne, L. Villeneuve, Y. Shen, F. Concilio |
Modeling of Tape Automated Bonding (TAB) for High Performance Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 2464-2467, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Rong Jiang 0002, Wenyin Fu, Charlie Chung-Ping Chen |
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10), pp. 1562-1571, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Zhengtao Yu 0002, Xun Liu |
Power Analysis of Rotary Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 150-155, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hao Yu 0001, Lei He 0001 |
A sparsified vector potential equivalent circuit model for massively coupled interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 105-108, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan |
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 603-608, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Woo Hyung Lee, Sanjay Pant, David T. Blaauw |
Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 131-136, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi |
Inductance model and analysis methodology for high-speed on-chip interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 10(6), pp. 730-745, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao 0001, Rajendran Panda, Sachin S. Sapatnekar |
A precorrected-FFT method for simulating on-chip inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 221-227, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Tao Lin, Lawrence T. Pileggi |
Throughput-driven IC communication fabric synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 274-279, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Phillip J. Restle, Albert E. Ruehli, Steven G. Walker |
Multi-GHz interconnect effects in microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001, pp. 93-97, 2001, ACM, 1-58113-347-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
full-wave analysis, simulation, interconnect, inductance, extraction, clock distribution, circuit-tuning |
19 | Atsushi Kamo, Takayuki Watanabe, Hideki Asai |
Simulation for the optimal placement of decoupling capacitors on printed circuit board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 727-730, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Mattan Kamon, Nuno Alexandre Marques, Jacob K. White 0001 |
FastPep: a fast parasitic extraction program for complex three-dimensional geometries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 456-460, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
electromagnetic modeling, packaging analysis, interconnect, model order reduction |
Displaying result #1 - #42 of 42 (100 per page; Change: )
|
|