Search results for "PFET"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
72	David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler	Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
72	Paul E. Hasler, Jeff Dugger	Correlation learning rule in floating-gate pFET synapses.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
72	Paul E. Hasler, Bradley A. Minch, Chris Diorio	Adaptive Circuits Using pFET Floating-Gate Devices.	ARVLSI	1999	DBLP DOI BibTeX RDF
53	Priti Gupta, Mukti Bansal, C. M. Markan	Neuromorphic Adaptable Ocular Dominance Maps.	PReMI	2007	DBLP DOI BibTeX RDF	Floating Gate pFET, WTA, ocular dominance, competitive learning, Feature maps
52	Paul E. Hasler, Arindam Basu, Sctt Kozil	Above Threshold pFET InjectionModeling intended for ProgrammingFloating-Gate Systems.	ISCAS	2007	DBLP DOI BibTeX RDF
33	Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya	Effect of Process Variation on the Performance of Phase Frequency Detector.	DFT	2006	DBLP DOI BibTeX RDF	Phase Frequency Detector (PFD), NFET, PFET, process variation, Monte Carlo simulation, Jitter, Phase noise
32	Kun Chen, Jingwen Yang, Chunlei Wu, Chen Wang, Min Xu, David Wei Zhang	Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications.	IEEE Access	2023	DBLP DOI BibTeX RDF
32	Xiaona Zhu, Rongzheng Ding, Ouwen Tao, Yage Zhao, Peishun Tang, David Wei Zhang, Ye Lu, Shaofeng Yu	A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
32	Md Nur K. Alam, Yusuke Higashi, Brecht Truijen, Ben Kaczer, Mihaela Ioana Popovici, Bj O'Sullivan, Philippe Roussel, Robin Degraeve, Marc M. Heyns, Jan Van Houdt	Insight to Data Retention loss in ferroelectric Hf0.5Zr0.5O2 pFET and nFET from simultaneous PV and IV measurements.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
32	Qingyou He, Liangqun Li	PFET: Multi-Vehicle Tracking with Pseudo-Feature Embeddings for Traffic Video Surveillance.	FUSION	2022	DBLP BibTeX RDF
32	Shimpei Yamaguchi, Liesbeth Witters, Jérôme Mitard, Geert Eneman, Geert Hellings, Andriy Hikavyy, Roger Loo, Naoto Horiguchi	Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET.	Microelectron. Reliab.	2018	DBLP DOI BibTeX RDF
32	Hanwool Jeong, Taewon Kim, Younghwi Yang, Taejoong Song, Gyu-Hong Kim, Hyo-Sig Won, Seong-Ook Jung	Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
32	Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine	A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells.	CICC	2015	DBLP DOI BibTeX RDF
32	Garima Kapur, C. M. Markan	Design of an analog field programmable RC oscillator using a floating gate PFET.	AHS	2010	DBLP DOI BibTeX RDF
32	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
32	Julian A. Bragg, Reid R. Harrison, Paul E. Hasler, Stephen P. DeWeerth	A floating-gate pFET based CMOS programmable analog memory cell array.	ISCAS	2000	DBLP DOI BibTeX RDF
20	Kanak Agarwal	On-die sensors for measuring process and environmental variations in integrated circuits.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	environmental variation, test structure, monitors, sensors, process variation, characterization
20	Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Design and analysis of ultra-thin-body SOI based subthreshold SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	poisson's equation, subthreshold SRAM, ultra-thin-body, soi, static noise margin
20	C. M. Markan, Priti Gupta	Neuromorphic building blocks for adaptable cortical feature maps.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
20	Christal Gordon, Amanda Preyer, Karolyn Babalola, Robert J. Butera, Paul E. Hasler	An artificial synapse for interfacing to biological neurons.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Thomas Pompl, Christian Schlünder, Martina Hommel, Heiko Nielen, Jens Schneider	Practical aspects of reliability analysis for IC designs.	DAC	2006	DBLP DOI BibTeX RDF	ESD, TDDB of intermetal dielectric, design-in reliability, gate oxide integrity, hot carrier stress, stress-induced voiding, NBTI, electromigration
20	Yanyi Liu Wong, Pamela Abshire, Marc H. Cohen	A 128×128 floating gate imager with self-adapting fixed pattern noise reduction.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
20	Shantanu Chakrabartty, Gert Cauwenberghs	Fixed-current method for programming large floating-gate arrays.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
20	Yanyi Liu Wong, Marc H. Cohen, Pamela Abshire	A 1.2 GHz adaptive floating gate comparator with 13-bit resolution.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Ravi Chawla, Guillermo J. Serrano, Daniel J. Allen, Angelo W. Pereira, Paul E. Hasler	Fully differential floating-gate programmable OTAs with novel common-mode feedback.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
20	Eric Liu Wong, Pamela Abshire, Marc H. Cohen	Floating gate comparator with automatic offset manipulation functionality.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
20	Christal Gordon, Paul E. Hasler	Biological learning modeled in an adaptive floating-gate system.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
20	C. S. Murthy, M. Gall	Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
20	Terence B. Hook	Automatic extraction of circuit models from layout artwork for a BiCMOS technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
20	Allen C.-H. Wu, Nels Vander Zanden, Daniel Gajski	A new algorithm for transistor sizing in CMOS circuits.	EURO-DAC	1990	DBLP DOI BibTeX RDF