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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 32 occurrences of 23 keywords
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Results
Found 48 publication records. Showing 48 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
94 | Michael D. Hutton |
Interconnect prediction for programmable logic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 125-131, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
interconnect prodiction, wireability, architecture, programmable logic device |
75 | Dewayne E. Perry, Jeff Kramer |
Architectural Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESPRIT ARES Workshop ![In: Development and Evolution of Software Architectures for Product Families, Second International ESPRIT ARES Workshop, Las Palmas de Gran Canaria, Spain, February 26-27, 1998, Proceedings, pp. 49-50, 1998, Springer, 3-540-64916-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
56 | Maurice Gagnaire, Mohamed Koubàa, Nicolas Puech |
Network Dimensioning under Scheduled and Random Lightpath Demands in All-Optical WDM Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 25(S-9), pp. 58-67, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | A. Abo Shosha, P. Reinhart, F. Rongen |
Reconfigurable PCI-Bus Interface (RPCI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 485-489, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
48 | Snezhana P. Kostova |
A PLDS Model of Pollution in Connected Water Reservoirs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
POSTA ![In: Positive Systems, Proceedings of the First Multidisciplinary International Symposium on Positive Systems: Theory and Applications (POSTA 2003), Rome, Italy, August 28-30, 2003, pp. 257-263, 2003, Springer, 3-540-40342-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Eric W. Johnson |
Extensive Introduction to VHDL and PLDs in the Sophomore Year. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 23-24, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
48 | Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio |
TOP: An Algorithm for Three-Level Optimization of PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 751, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
48 | Jason Helge Anderson, Stephen Dean Brown |
Technology Mapping for Large Complex PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 698-703, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
48 | Niklaus Wirth |
The Language Lola, FPGAs and PLDs in Teaching Digital Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ershov Memorial Conference ![In: Perspectives of System Informatics, Second International Andrei Ershov Memorial Conference, Akademgorodok, Novosibirsk, Russia, June 25-28, 1996, Proceedings, pp. 2-20, 1996, Springer, 3-540-62064-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
38 | Adrian J. Hilton, Jon G. Hall |
High-Integrity Interfacing to Programmable Logic with Ada. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ada-Europe ![In: Reliable Software Technologies - Ada-Europe 2004, 9th Ada-Europe International Conference on Reliable Software Technologies, Palma de Mallorca, Spain, June 14-18, 2004, Proceedings, pp. 249-260, 2004, Springer, 3-540-22011-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Valeri Tomachev |
The PLD-Implementation of Boolean Function Characterized by Minimum Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 481-484, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Wenyi Feng, Sinan Kaptanoglu |
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 6:1-6:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT |
33 | Wenyi Feng, Sinan Kaptanoglu |
Designing efficient input interconnect blocks for LUT clusters using counting and entropy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007, pp. 23-32, 2007, ACM, 978-1-59593-600-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT |
29 | Chaofeng Yuan, Yuelei Xu, Qing Zhou |
PLDS-SLAM: Point and Line Features SLAM in Dynamic Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Remote. Sens. ![In: Remote. Sens. 15(7), pp. 1893, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Karnika Shivhare, Rushikesh K. Joshi |
Process Line Diagrams (PLDs): An Approach for Modular Process Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISEC ![In: 16th Innovations in Software Engineering Conference, ISEC2023, Allahabad, India, February 23-25, 2023, pp. 13:1-13:11, 2023, ACM, 979-8-4007-0064-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Tommaso Addabbo, Ada Fort, Riccardo Moretti, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque |
Lightweight True Random Bit Generators in PLDs: Figures of Merit and Performance Comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Tsutomu Maruyama, Yoshiki Yamaguchi, Yasunori Osana |
Programmable Logic Devices (PLDs) in Practical Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 179-205, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Tommaso Addabbo, Ada Fort, Marco Mugnaini, Valerio Vignoli, Miguel Garcia-Bosque |
Digital Nonlinear Oscillators in PLDs: Pitfalls and Open Perspectives for a Novel Class of True Random Number Generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-5, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | G. Sumathi, L. Srivani, D. Thirugnana Murthy, Anish Kumar, K. Madhusoodanan |
Hardware Obfuscation Using Different Obfuscation Cell Structures for PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SG-CRC ![In: A Systems Approach to Cyber Security - Proceedings of the 2nd Singapore Cyber-Security R&D Conference (SG-CRC 2017), Singapore, February 21-22, 2017, pp. 143-157, 2017, IOS Press, 978-1-61499-743-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Hiroki Nishiyama 0003, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko |
An ILP-Based Optimal Circuit Mapping Method for PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014, pp. 251-256, 2014, IEEE Computer Society, 978-0-7695-5208-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Marian Gilewski |
An Application of PLDs in Diode Laser Drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDeS ![In: 12th IFAC Conference on Programmable Devices and Embedded Systems, PDeS 2013, Ostrava, Czech Republic, September 25-27, 2013., pp. 304-307, 2013, International Federation of Automatic Control, 978-3-902823-53-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Min Feng 0001, Changhui Lin, Rajiv Gupta 0001 |
PLDS: Partitioning linked data structures for parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 8(4), pp. 38:1-38:21, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Bashar Al-Khalifa |
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. Arab J. Inf. Technol. ![In: Int. Arab J. Inf. Technol. 7(2), pp. 124-128, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
29 | Monica Figueiredo, Rui L. Aguiar |
Performance of 155Mbps clock/data recovery circuits on heavy loaded PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003, pp. 511-514, 2003, IEEE, 0-7803-8163-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Guy G. Lemieux, Paul Leventis, David M. Lewis |
Generating highly-routable sparse crossbars for PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 155-164, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Jason Cong, Songjie Xu |
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2000, Asia and South Pacific Design Automation Conference 2000, Yokohama, Japan, pp. 157-162, 2000, ACM, 0-7803-5974-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Alan E. Clapp, Thomas L. Harman |
Combining microcontroller units and PLDs for best system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 14(2), pp. 70-78, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | André Klindworth |
A Tool-Set for Simulating Altera-PLDs Using VHDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, pp. 306-308, 1994, Springer, 3-540-58419-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
29 | Martin Bolton |
Practical Programmable Circuits: A Guide to PLDs, State Machines and Microcontrollers: James D Broesch Academic Press, London, UK (1991) ISBN 0 12 134885 7, £34, pp 286. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 17(7), pp. 435, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Chris Jay |
VHDL and synthesis tools provide a generic design entry platform into FPGAs, PLDs and ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 17(7), pp. 391-398, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Serafín Pérez, Enrique Mandado, Jacobo Ruiz de Ojeda |
Logic controllers design methods using advanced PLDS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 37(1-5), pp. 215-219, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
29 | Günter Biehl |
Overview of Complex Array-Based PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers, pp. 1-10, 1992, Springer, 3-540-57091-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
29 | Abdul A. Malik, David Harrison, Robert K. Brayton |
Three-Level Decomposition with Application to PLDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 628-633, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Meredith McLendon, Ann McNamara, Tim McLaughlin, Ravindra Dwivedi |
Lions and tigers and bears: investigating cues for expressive creature motion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGGRAPH Posters ![In: International Conference on Computer Graphics and Interactive Techniques, SIGGRAPH 2010, Los Angeles, California, USA, July 26-30, 2010, Poster Proceedings, pp. 10:1, 2010, ACM, 978-1-4503-0393-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
19 | Meredith McLendon, Ann McNamara, Tim McLaughlin, Ravindra Dwivedi |
Using eye tracking to investigate important cues for representative creature motion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETRA ![In: Proceedings of the 2010 Symposium on Eye-Tracking Research & Applications, ETRA 2010, Austin, Texas, USA, March 22-24, 2010, pp. 85-88, 2010, ACM, 978-1-60558-994-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
point-light display, animation, perception, eyetracking |
19 | Hassan Farhat |
Integrating electronics in computer science under curricula constraints, a comparative study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 140-144, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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19 | Jin-Wei Tioh, Rashmi Bahuguna, Nathan A. VanderHorn, Mani Mina, Robert J. Weber, Arun K. Somani |
Reprogrammable high-speed platform : Bridging the gap between research, education and engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 145-147, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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19 | Issam W. Damaj |
Higher-Level Hardware Synthesis of the KASUMI Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 22(1), pp. 60-70, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
parallel algorithms, methodology, formal models, data encryption, gate array |
19 | Seung-Jun Lee, Chunsoo Ahn, Jitae Shin |
Control Parameter Setting of IEEE 802.11e for Proportional Loss Rate Differentiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (1) ![In: Computational Science - ICCS 2006, 6th International Conference, Reading, UK, May 28-31, 2006, Proceedings, Part I, pp. 952-955, 2006, Springer, 3-540-34379-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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19 | Sandip Kundu, T. M. Mak, Rajesh Galivanche |
Trends in manufacturing test methods and their implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 679-687, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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19 | Christian Siemers, Volker Winterstein |
Modelling Programmable Logic Devices and Reconfigurable, Microprocessor-Related Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 188, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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19 | Kenneth Yan |
Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 231-234, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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19 | Artur Chojnacki, Lech Józwiak |
High-quality FPGA Designs through Functional Decomposition with Sub-function Input Support Selection Based on Information Relationship Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 409-414, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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19 | Artur Chojnacki, Lech Józwiak |
Multi-Valued Sub-Function Encoding in Functional Decomposition Based on Information Relationships Measures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 30th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings, pp. 83-90, 2000, IEEE Computer Society, 0-7695-0692-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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19 | Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung |
Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 20-24, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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19 | Loc Bao Nguen, Marek A. Perkowski, Lech Józwiak |
Design of Self-Synchronized Component FSMs for Self-Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10253-10260, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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19 | David Ashen, Fred J. Meyer, Nohpill Park, Fabrizio Lombardi |
Testing of programmable logic devices (PLD) with faulty resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 76-84, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
faulty resources, routing resources, built-in self-test schemes, parity chain, one-dimensional arrays, active routing devices, interconnection channels, input/output lines, logic testing, fault model, fault coverage, multiple faults, programmable logic devices, programmable logic devices |
19 | C. Hwa Chang, Hammad K. Azzam |
A weighted technique for programmable logic devices minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 267-274, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
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