Search results for "POWER5"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson	Design and implementation of the POWER5 microprocessor.	DAC	2004	DBLP DOI BibTeX RDF	POWER5, simultaneous multi-threading (SMT), clock gating, power reduction, microprocessor design, temperature sensor
72	Ibrahim Hur, Calvin Lin	Memory Prefetching Using Adaptive Stream Detection.	MICRO	2006	DBLP DOI BibTeX RDF
66	Dave W. Victor, John M. Ludden, Richard D. Peterson, Bradley S. Nelson, W. Keith Sharp, James K. Hsu, Bing-Lun Chu, Michael L. Behm, Rebecca M. Gott, Audre D. Romonosky, Steven R. Farago	Functional verification of the POWER5 microprocessor and POWER5 multiprocessor systems.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
51	Subhash Saini, Dale Talcott, Dennis C. Jespersen, M. Jahed Djomehri, Haoqiang Jin, Rupak Biswas	Scientific application-based performance comparison of SGI Altix 4700, IBM POWER5+, and SGI ICE 8200 supercomputers.	SC	2008	DBLP DOI BibTeX RDF
51	Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler	IBM Power5 Chip: A Dual-Core Multithreaded Processor.	IEEE Micro	2004	DBLP DOI BibTeX RDF
36	Ciji Isen, Lizy K. John, Eugene John	A Tale of Two Processors: Revisiting the RISC-CISC Debate.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF
36	Seetharami R. Seelam, I-Hsin Chung, Guojing Cong, Hui-Fang Wen, David J. Klepacki	Workload Performance Characterization of DARPA HPCS Benchmarks.	HPCC	2008	DBLP DOI BibTeX RDF
36	Ibrahim Hur, Calvin Lin	Memory scheduling for modern microprocessors.	ACM Trans. Comput. Syst.	2007	DBLP DOI BibTeX RDF	adaptive history-based scheduling, memory scheduling, Memory system performance
36	Shoaib Kamil 0001, Kaushik Datta, Samuel Williams 0001, Leonid Oliker, John Shalf, Katherine A. Yelick	Implicit and explicit optimizations for stencil computations.	Memory System Performance and Correctness	2006	DBLP DOI BibTeX RDF
33	Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	SMT Malleability in IBM POWER5 and POWER6 Processors.	IEEE Trans. Computers	2013	DBLP DOI BibTeX RDF
33	Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero	Software-Controlled Priority Characterization of POWER5 Processor.	ISCA	2008	DBLP DOI BibTeX RDF
33	Tomoaki Hirota, Hisayasu Kuroda	Implementation of Integer Multiplication in Multiple-Precision on POWER5+ Architecture.	CSC	2008	DBLP BibTeX RDF
33	Vipin Sachdeva, Evan Speight, Mark W. Stephenson, Lei Chen	Characterizing and Improving the Performance of Bioinformatics Workloads on the POWER5 Architecture.	IISWC	2007	DBLP DOI BibTeX RDF
33	Paul Mackerras, Thomas S. Mathews, Randal C. Swanberg	Operating system exploitation of the POWER5 system.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
33	William J. Armstrong, Richard L. Arndt, David C. Boutcher, Robert G. Kovacs, David Larson, Kyle A. Lucke, Naresh Nayar, Randal C. Swanberg	Advanced virtualization capabilities of POWER5 systems.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
33	Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner	POWER5 system microarchitecture.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
33	Harry M. Mathis, Alex E. Mericas, John D. McCalpin, Richard J. Eickemeyer, Steven R. Kunkel	Characterization of simultaneous multithreading (SMT) efficiency in POWER5.	IBM J. Res. Dev.	2005	DBLP DOI BibTeX RDF
31	Joefon Jann, R. Sarma Burugula, Niteesh Dubey, Pratap Pattnaik	End-to-end performance of commercial applications in the face of changing hardware.	ACM SIGOPS Oper. Syst. Rev.	2008	DBLP DOI BibTeX RDF	AIX, POWER5+, POWER6, WebSphere
31	Ibrahim Hur, Calvin Lin	Adaptive History-Based Memory Schedulers for Modern Processors.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Memory schedulers, IBM Power5, processors, DRAM, memory bandwidth
18	Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi	Dynamic heterogeneity and the need for multicore virtualization.	ACM SIGOPS Oper. Syst. Rev.	2009	DBLP DOI BibTeX RDF
18	Ganesh Bikshandi, José G. Castaños, Sreedhar B. Kodali, V. Krishna Nandivada, Igor Peshansky, Vijay A. Saraswat, Sayantan Sur, Pradeep Varma, Tong Wen	Efficient, portable implementation of asynchronous multi-place programs.	PPoPP	2009	DBLP DOI BibTeX RDF	apgas, hpc challenge, spmd, compiler, stream, hpc, asynchrony, random access, runtime, pgas, x10, fft
18	Kevin Reick, Pia N. Sanda, Scott B. Swaney, Jeffrey W. Kellington, Michael J. Mack, Michael S. Floyd, Daniel Henderson	Fault-Tolerant Design of the IBM Power6 Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, fault isolation, RAS, instruction retry, Hot Chips 19
18	Marc González 0001, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen 0001, Zehra Sura, Tao Zhang, Kevin O'Brien, Kathryn M. O'Brien	Hybrid access-specific software cache techniques for the cell BE architecture.	PACT	2008	DBLP DOI BibTeX RDF	memory classification, OpenMP, compiler optimizations, local memories, software cache
18	Lin Qiao, Vijayshankar Raman, Inderpal Narang, Prashant Pandey 0005, David D. Chambliss, Gene Fuh, James A. Ruddy, Ying-Lin Chen, Kou-Horng Yang, Fen-Ling Ling	Integration of Server, Storage and Database Stack: Moving Processing Towards Data.	ICDE	2008	DBLP DOI BibTeX RDF
18	Ibrahim Hur, Calvin Lin	A comprehensive approach to DRAM power management.	HPCA	2008	DBLP DOI BibTeX RDF
18	Mackale Joyner, Zoran Budimlic, Vivek Sarkar, Rui Zhang	Array optimizations for parallel implementations of high productivity languages.	IPDPS	2008	DBLP DOI BibTeX RDF
18	Priya Nagpurkar, William Horn 0001, U. Gopalakrishnan, Niteesh Dubey, Joefon Jann, Pratap Pattnaik	Workload characterization of selected JEE-based Web 2.0 applications.	IISWC	2008	DBLP DOI BibTeX RDF
18	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.	ICPP	2008	DBLP DOI BibTeX RDF
18	Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero	A dynamic scheduler for balancing HPC applications.	SC	2008	DBLP DOI BibTeX RDF
18	Priya Nagpurkar, Harold W. Cain, Mauricio J. Serrano, Jong-Deok Choi, Chandra Krintz	Call-chain Software Instruction Prefetching in J2EE Server Applications.	PACT	2007	DBLP DOI BibTeX RDF
18	Leonid Oliker, Andrew Canning, Jonathan Carter, Costin Iancu, Michael Lijewski, Shoaib Kamil 0001, John Shalf, Hongzhang Shan, Erich Strohmaier, Stéphane Ethier, Tom Goodale	Scientific Application Performance on Candidate PetaScale Platforms.	IPDPS	2007	DBLP DOI BibTeX RDF
18	Michael D. Powell, T. N. Vijaykumar	Resource area dilation to reduce power density in throughput servers.	ISLPED	2007	DBLP DOI BibTeX RDF	throughput servers, SMT, power density
18	Gabriel Tanase, Chidambareswaran Raman, Mauro Bianco, Nancy M. Amato, Lawrence Rauchwerger	Associative Parallel Containers in STAPL.	LCPC	2007	DBLP DOI BibTeX RDF
18	Julian Borrill, Leonid Oliker, John Shalf, Hongzhang Shan	Investigation of leading HPC I/O performance using a scientific-application derived benchmark.	SC	2007	DBLP DOI BibTeX RDF
18	David K. Tam, Reza Azimi, Michael Stumm	Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors.	EuroSys	2007	DBLP DOI BibTeX RDF	cache behavior, detecting sharing, performance monitoring unit, single-chip multiprocessors, thread placement, resource allocation, CMP, multithreading, sharing, SMP, simultaneous multithreading, SMT, shared caches, cache locality, thread scheduling, thread migration, hardware performance monitors, hardware performance counters, affinity scheduling
18	Michael L. Welcome, Charles A. Rendleman, Leonid Oliker, Rupak Biswas	Performance characteristics of an adaptive mesh refinement calculation on scalar and vector platforms.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	IBM power3 and power4, SGI, altix, cray X1E, high end computing, hyperCLaw framework, integrated performance monitoring
18	Carlos García 0001, Manuel Prieto 0001, Javier Setoain, Francisco Tirado	Enhancing the Performance of Multigrid Smoothers in Simultaneous Multithreading Architectures.	VECPAR	2006	DBLP DOI BibTeX RDF
18	Jonathan Carter, Leonid Oliker, John Shalf	Performance Evaluation of Scientific Applications on Modern Parallel Vector Systems.	VECPAR	2006	DBLP DOI BibTeX RDF
18	Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
18	Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler	Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.	HPCA	2005	DBLP DOI BibTeX RDF
18	Ibrahim Hur, Calvin Lin	Adaptive History-Based Memory Schedulers.	MICRO	2004	DBLP DOI BibTeX RDF
18	Wolfgang Roesner	What Is beyond the RTL Horizon for Microprocessor and System Design?	CHARME	2003	DBLP DOI BibTeX RDF