Search results for "POWER6"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
94	Kevin Reick, Pia N. Sanda, Scott B. Swaney, Jeffrey W. Kellington, Michael J. Mack, Michael S. Floyd, Daniel Henderson	Fault-Tolerant Design of the IBM Power6 Microprocessor.	IEEE Micro	2008	DBLP DOI BibTeX RDF	fault tolerance, reliability, fault isolation, RAS, instruction retry, Hot Chips 19
43	Martin Sandrieser, Sabri Pllana, Siegfried Benkner	Evaluation of the SUN UltraSparc T2+ Processor for Computational Science.	ICCS (1)	2009	DBLP DOI BibTeX RDF	Sun UltraSparc T2+, Niagara2, Evaluation, Computational Science
36	Joefon Jann, R. Sarma Burugula, Niteesh Dubey, Pratap Pattnaik	End-to-end performance of commercial applications in the face of changing hardware.	ACM SIGOPS Oper. Syst. Rev.	2008	DBLP DOI BibTeX RDF	AIX, POWER5+, POWER6, WebSphere
30	Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero	SMT Malleability in IBM POWER5 and POWER6 Processors.	IEEE Trans. Computers	2013	DBLP DOI BibTeX RDF
30	Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose	Characterizing Power and Temperature Behavior of POWER6-Based System.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2011	DBLP DOI BibTeX RDF
30	Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose	Power and thermal characterization of POWER6 system.	PACT	2010	DBLP DOI BibTeX RDF
30	Harold W. Cain, Priya Nagpurkar	Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor.	ISPASS	2010	DBLP DOI BibTeX RDF
30	Benjamin Stolt, Yonatan Mittlefehldt, Sanjay Dubey, Gaurav Mittal, Mike Lee, Joshua Friedrich, Eric Fluhr	Design and Implementation of the POWER6 Microprocessor.	IEEE J. Solid State Circuits	2008	DBLP DOI BibTeX RDF
30	Pia N. Sanda, Jeffrey W. Kellington, Prabhakar Kudva, Ronald N. Kalla, Ryan B. McBeth, Jerry Ackaret, Ryan Lockwood, John Schumann, Christopher R. Jones	Soft-error resilience of the IBM POWER6 processor.	IBM J. Res. Dev.	2008	DBLP DOI BibTeX RDF
30	Carl A. Bender, Pia N. Sanda, Prabhakar Kudva, Ricardo Mata, Vikas Pokala, Ryan Haraden, Matthew Schallhorn	Soft-error resilience of the IBM POWER6 processor input/output subsystem.	IBM J. Res. Dev.	2008	DBLP DOI BibTeX RDF
30	Peilin Song, Stephen Ippolito, Franco Stellari, John Sylvestri, Tim Diemoz, George Smith, Paul Muench, Norm James, Seongwon Kim, Hector Saenz	Optical Diagnostics for IBM POWER6- Microprocessor.	ITC	2008	DBLP DOI BibTeX RDF
30	Tung N. Pham, Frances Clougherty, Gerard Salem, James M. Crafts, Jon Tetzloff, Pamela Moczygemba, Timothy M. Skergan	Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors.	ITC	2008	DBLP DOI BibTeX RDF
30	Lee Eisen, John Wesley Ward III, Hans-Werner Tast, Nicolas Mäding, Jens Leenstra, Silvia M. Müller, Christian Jacobi 0002, Jochen Preiss, Eric M. Schwarz, Steven R. Carlough	IBM POWER6 accelerators: VMX and DFU.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Brian W. Curran, Eric Fluhr, Jose Paredes, Leon J. Sigal, Joshua Friedrich, Yiu-Hing Chan, Charlie Hwang	Power-constrained high-frequency circuits for the IBM POWER6 microprocessor.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Hye-Young McCreary, Martha A. Broyles, Michael S. Floyd, Andrew J. Geissler, Steven P. Hartman, Freeman L. Rawson III, Todd J. Rosedahl, Juan C. Rubio, Malcolm S. Ware	EnergyScale for IBM POWER6 microprocessor-based systems.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Michael J. Mack, Wolfram Sauer, Scott B. Swaney, Bruce G. Mealey	IBM POWER6 reliability.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Hung Q. Le, William J. Starke, J. Stephen Fields, Francis P. O'Connell, Dung Q. Nguyen, Bruce J. Ronchetti, Wolfram Sauer, Eric M. Schwarz, Michael T. Vaden	IBM POWER6 microarchitecture.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Donald W. Plass, Yuen H. Chan	IBM POWER6 SRAM arrays.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Rex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas E. Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams	IBM POWER6 microprocessor physical design and design methodology.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Michael S. Floyd, Soraya Ghiasi, Tom W. Keller, Karthick Rajamani, Freeman L. Rawson III, Juan C. Rubio, Malcolm S. Ware	System power management support in the IBM POWER6 microprocessor.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	William J. Armstrong, Richard L. Arndt, Timothy R. Marchini, Naresh Nayar, Wolfram Sauer	IBM POWER6 partition mobility: Moving virtual servers seamlessly between physical systems.	IBM J. Res. Dev.	2007	DBLP DOI BibTeX RDF
30	Norman K. James, Phillip J. Restle, Joshua Friedrich, Bill Huott, Bradley D. McCredie	Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor.	ISSCC	2007	DBLP DOI BibTeX RDF
30	Joshua Friedrich, Bradley D. McCredie, Norman K. James, Bill Huott, Brian W. Curran, Eric Fluhr, Gaurav Mittal, Eddie Chan, Yuen H. Chan, Donald W. Plass, Sam G. Chu, Hung Q. Le, Leo Clark, John R. Ripley, Scott A. Taylor, Jack DiLullo, Mary Yvonne Lanzerotti	Design of the Power6 Microprocessor.	ISSCC	2007	DBLP DOI BibTeX RDF
30	Eric M. Schwarz, Steven R. Carlough	Power6 Decimal Divide.	ASAP	2007	DBLP DOI BibTeX RDF
30	Brian W. Curran, Bradley D. McCredie, Leonid Sigal, Eric M. Schwarz, Bruce M. Fleischer, Yuen H. Chan, D. Webber, Vaden Vaden, A. Goyal	4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.	ISSCC	2006	DBLP DOI BibTeX RDF
30	Michael G. R. Thomson, Phillip J. Restle, Norman K. James	A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor.	ISSCC	2006	DBLP DOI BibTeX RDF
21	Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito 0001, Alexandru Nicolau, Alexander V. Veidenbaum, Utpal Banerjee, Constantine D. Polychronopoulos	Exploitation of nested thread-level speculative parallelism on multi-core systems.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	performance, thread-level speculation
21	Liang-Kai Wang, Michael J. Schulte, John D. Thompson, Nandini Jairam	Hardware Designs for Decimal Floating-Point Addition and Related Operations.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
21	Takeshi Ogasawara	NUMA-aware memory manager with dominant-thread-based copying GC.	OOPSLA	2009	DBLP DOI BibTeX RDF	java, cc-NUMA
21	Sameh Sharkawi, Don DeSota, Raj Panda, Rajeev Indukuru, Stephen Stevens, Valerie E. Taylor, Xingfu Wu	Performance projection of HPC applications using SPEC CFP2006 benchmarks.	IPDPS	2009	DBLP DOI BibTeX RDF
21	Friman Sánchez, Alex Ramírez, Mateo Valero	Quantitative analysis of sequence alignment applications on multiprocessor architectures.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	bioinformatics applications, parallel architectures, multiprocessor architectures, sequence comparison
21	Emmanuel Agullo, Bilel Hadri, Hatem Ltaief, Jack J. Dongarra	Comparative study of one-sided factorizations with multiple software packages on multi-core hardware.	SC	2009	DBLP DOI BibTeX RDF
21	Raj Amirtharajah, John R. Mashey	Guest Editors' Introduction: Hot Chips 19.	IEEE Micro	2008	DBLP DOI BibTeX RDF	wireless HD, fault tolerance, mobile computing, low-power, GPU, computer architecture, microprocessors, mainframe computing, Hot Chips 19
21	Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W. Kellington, John Schumann, Pia N. Sanda	Statistical Fault Injection.	DSN	2008	DBLP DOI BibTeX RDF
21	Carmelo Acosta, Francisco J. Cazorla, Alex Ramírez, Mateo Valero	MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.	ICPP	2008	DBLP DOI BibTeX RDF
21	Ling Zhang, Wenjian Yu, Yulei Zhang 0002, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng	Low Power Passive Equalizer Design for Computer Memory Links.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	passive equalization, low power
21	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF