Search results for "PWL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	Jie Liu, Junan Lu, Xiaoqun Wu	Bridge the gap between the PWL Lorenz and PWL Chen's system.	ICARCV	2004	DBLP DOI BibTeX RDF
109	Jun Chen 0008, Lei He 0001	Piecewise linear model for transmission line with capacitive loading and ramp input.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
91	Víctor Manuel Jimenez-Fernandez, Luis Hernández-Martínez, Arturo Sarmiento-Reyes	A method for finding the DC solution regions in piecewise-linear networks.	ISCAS	2006	DBLP DOI BibTeX RDF
79	Jerzy J. Dabrowski, Andrzej Pulka	Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique.	DATE	1999	DBLP DOI BibTeX RDF
72	Víctor Manuel Jimenez-Fernandez, Luis Hernández-Martínez, Arturo Sarmiento-Reyes	Decomposed piecewise-linear models by hyperplanes unbending.	ISCAS	2006	DBLP DOI BibTeX RDF
72	Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin	A comparative study of power efficient SRAM designs.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF	low power, decoder, SRAM
61	Martin Di Federico, Pedro Julián, Tomaso Poggi, Marco Storace	A Simplicial PWL Integrated Circuit Realization.	ISCAS	2007	DBLP DOI BibTeX RDF
55	Alicia Manthe, Zhao Li, C.-J. Richard Shi	Symbolic analysis of analog circuits with hard nonlinearity.	DAC	2003	DBLP DOI BibTeX RDF	PWL, circuit nonlinearity, symbolic analysis
54	M. S. Bhat 0001, S. Rekha, H. S. Jamadagni	Extrinsic Analog Synthesis Using Piecewise Linear Current-Mode Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
54	Jun Chen 0008, Lei He 0001	Modeling of coplanar waveguide for buffered clock tree.	ASP-DAC	2004	DBLP DOI BibTeX RDF
54	Pedro Julián, Radu Dogaru, Leon O. Chua	Exploiting piecewise linear features: multinested and simplicial cellular neural/nonlinear networks.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
43	Jose L. Figueroa, Juan E. Cousseau, Rui J. P. de Figueiredo	A piecewise linear dynamical functional artificial neural network (PWL-DFANN) for nonlinear adaptive time series prediction.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
43	Marco Storace, Pedro Julián, Mauro Parodi	Towards the circuit implementation of the Hodgkin-Huxley neuron model: A PWL approach.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
43	Pedro Julián, Alfredo C. Desages, Belén D'Amico	Orthonormal high level canonical PWL functions.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
36	Gabriel H. Loh, Daniel A. Jiménez	Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Computer architecture, Branch prediction
36	Luigi Iannelli, Francesco Vasca	Computation of limit cycles and forced oscillations in discrete-time piecewise linear feedback systems through a complementarity approach.	CDC	2008	DBLP DOI BibTeX RDF
36	Sudip K. Mazumder, Kaustuva Acharya, Muhammad Tahir 0002	Network reconfiguration of distributed controlled homogenous power inverter network using composite Lyapunov function based reachability bound.	SCSC	2007	DBLP BibTeX RDF	piecewise linear systems, reaching conditions, switching power converters, linear matrix inequality, Markov-chain model, Lyapunov stability
36	Pablo Echevarria, M. Victoria Martínez, Javier Echanobe, Inés del Campo, José Manuel Tarela	Digital Hardware Implementation of High Dimensional Fuzzy Systems.	WILF	2007	DBLP DOI BibTeX RDF
36	Kiyotaka Yamamura, Takehisa Kitakawa	Finding all solutions of piecewise-linear resistive circuits using the simplex method.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
36	Lorenzo Repetto, Marco Storace, Mauro Parodi	A procedure for the piecewise-linear approximation of the resistive part of a cellular nonlinear network.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
36	Victor M. Preciado	Piecewise-Linear Approximation of Any Smooth Output Function on the Cellular Neural Network.	ICANN	2002	DBLP DOI BibTeX RDF
25	José Luis Echenausía-Monroy, S. Jafari, Guillermo Huerta-Cuéllar, Héctor Eduardo Gilardi Velázquez	Predicting the Emergence of Multistability in a Monoparametric PWL System.	Int. J. Bifurc. Chaos	2022	DBLP DOI BibTeX RDF
25	Yufei Zhang 0003	Data for an efficient PWL memristor model.		2022	DOI RDF
25	Ernesto Zambrano-Serrano, Jesús M. Muñoz-Pacheco, Fernando E. Serrano, Luis Abraham Sánchez-Gaspariano, Christos K. Volos	Experimental verification of the multi-scroll chaotic attractors synchronization in PWL arbitrary-order systems using direct coupling and passivity-based control.	Integr.	2021	DBLP DOI BibTeX RDF
25	Fei Lyu 0002, Zhelong Mao, Jin Zhang, Yu Wang 0161, Yuanyong Luo	PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
25	Ning Wang 0015, Guoshan Zhang, Houzhen Li	Parametric Control for Multi-Scroll Attractor Generation via Nested Sine-PWL Function.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
25	Anirban Dutta, Ashishkumar Prabhakar Gudmalwar, Ch. V. Rama Rao	Performance analysis of ASR system in hybrid DNN-HMM framework using a PWL euclidean activation function.	Frontiers Comput. Sci.	2021	DBLP DOI BibTeX RDF
25	Vantruong Nguyen, Jueping Cai, Linyu Wei, Jie Chu	Neural Networks Probability-Based PWL Sigmoid Function Approximation.	IEICE Trans. Inf. Syst.	2020	DBLP DOI BibTeX RDF
25	Yan Fu, Deming Kong, Haiyun Xin, Meihua Bi, Shi Jia, Kuo Zhang, Weisheng Hu, Hao Hu	Computationally Efficient 120 Gb/s/λ PWL Equalized 2D-TCM-PAM8 in Dispersion Unmanaged DML-DD System.	OFC	2020	DBLP BibTeX RDF
25	Andres Anzo-Hernández, Eric Campos-Cantón, Matthew Nicol	Itinerary synchronization between PWL systems coupled with unidirectional links.	Commun. Nonlinear Sci. Numer. Simul.	2019	DBLP DOI BibTeX RDF
25	Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu	Tunable Neuron With PWL Approximation Based on the Minimum Operator.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
25	Carlos Hernández-Mejía, Delia Torres-Muñoz	PWL Window Function for Nonlinear Memristive Systems.	CONIELECOMP	2019	DBLP DOI BibTeX RDF
25	Mohammad Radpour, Sayed Masoud Sayedi	SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor.	Integr.	2018	DBLP DOI BibTeX RDF
25	Oscar J. Cinco-Izquierdo, Maria Teresa Sanz, Luis Hernández 0005, Carlos Aristoteles De la Cruz-Blas	CMOS current-mode PWL implementation using MAX and MIN operators.	ISCAS	2017	DBLP DOI BibTeX RDF
25	Ernesto Zambrano-Serrano, Jesús M. Muñoz-Pacheco, Eric Campos-Cantón	Circuit synthesis of an incommensurate fractional order multi-scroll PWL chaotic system.	MOCAST	2017	DBLP DOI BibTeX RDF
25	D. Moro-Frías, Carlos Aristoteles De la Cruz-Blas, María Teresa Sanz-Pascual	PWL Current-Mode CMOS Exponential Circuit Based on Maximum Operator.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
25	Fu-Hsin Chen, Ming-Chang Yang, Yuan-Hao Chang 0001, Tei-Wei Kuo	PWL: a progressive wear leveling to minimize data migration overheads for nand flash devices.	DATE	2015	DBLP BibTeX RDF
25	Luis Benadero, Vanessa Moreno-Font, Abdelali El Aroudi	Unfolding nonsmooth bifurcation Patterns in a 1-d PWL Map as a Model of a Single-inductor Two-output DC-DC Switching Converter.	Int. J. Bifurc. Chaos	2013	DBLP DOI BibTeX RDF
25	M. H. McCullough, Herbert H. C. Iu, B. Muthuswamy	Chaotic behaviour in a three element memristor based circuit using fourth order polynomial and PWL nonlinearity.	ISCAS	2013	DBLP DOI BibTeX RDF
25	Stefano Pastore, Amedeo Premoli	A unified set-theoretic approach to the analysis of PWL resistive circuits and composite N-ports.	Int. J. Circuit Theory Appl.	2011	DBLP DOI BibTeX RDF
25	Junaid M. Khan, Shuning Wang	Lattice PWL Modeling of separable Convex Functions and its Application to the Vehicle following Problem.	Inf. Technol. Control.	2011	DBLP DOI BibTeX RDF
25	Laura Gardini, Fabio Tramontana	Border Collision bifurcations in 1D PWL Map with One Discontinuity and Negative Jump: Use of the First Return Map.	Int. J. Bifurc. Chaos	2010	DBLP DOI BibTeX RDF
25	Martin Di Federico, Pedro Julián, Pablo Sergio Mandolesi, Andreas G. Andreou	PWL cores for nonlinear array processing.	ISCAS	2010	DBLP DOI BibTeX RDF
25	D. Moro-Frías, María Teresa Sanz-Pascual, Carlos Aristoteles De la Cruz-Blas	Linear-in-dB Variable Gain Amplifier with PWL exponential gain control.	ISCAS	2010	DBLP DOI BibTeX RDF
25	Ehsan Rasekh, Iman Rasekh, Mohammad Eshghi	PWL approximation of hyperbolic tangent and the first derivative for VLSI implementation.	CCECE	2010	DBLP DOI BibTeX RDF
25	Stefan LeBel, Luis Rodrigues	PWL and PWA ℋ∞ controller synthesis for uncertain PWA slab systems: LMI approach.	Int. J. Control	2009	DBLP DOI BibTeX RDF
25	Stefano Pastore	Fast and Efficient Search for All DC Solutions of PWL Circuits by Means of Oversized Polyhedra.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
25	Daniele Linaro, Marco Righero, Mario Biey, Marco Storace	Synchronization Properties in Networks of Hindmarsh-Rose Neurons and their PWL Approximations with Linear Symmetric Coupling.	ISCAS	2009	DBLP DOI BibTeX RDF
25	Shukai Duan, Lidan Wang 0001	Circuitry Implementation for a Simple Delayed Chaotic Neural Model with PWL Function.	ICNC (3)	2008	DBLP DOI BibTeX RDF
25	Daniele Linaro, Marco Storace	A method based on a genetic algorithm to find PWL approximations of multivariate nonlinear functions.	ISCAS	2008	DBLP DOI BibTeX RDF
25	Marco Storace, Federico Bizzarri	Towards Accurate PWL Approximations of Parameter-Dependent Nonlinear Dynamical Systems With Equilibria and Limit Cycles.	IEEE Trans. Circuits Syst. I Regul. Pap.	2007	DBLP DOI BibTeX RDF
25	Eduardo Mojica-Nava, Alain Gauthier, Naly Rakoto-Ravalontsalama	Probing Control for PWL Approximation of Nonlinear Cellular Growth.	CCA	2007	DBLP DOI BibTeX RDF
25	Federico Bizzarri, Daniele Linaro, Marco Storace	PWL approximation of the Hindmarsh-Rose neuron model in view of its circuit implementation.	ECCTD	2007	DBLP DOI BibTeX RDF
25	Alessio Boggiano, Simone Delfitto, Tomaso Poggi, Marco Storace	FPGA implementation of a new scheme for the circuit realization of PWL functions.	ECCTD	2007	DBLP DOI BibTeX RDF
25	Dan Sui, Chong Jin Ong	Computation of Polytopal Invariant Sets of PWL Systems with Bounded Disturbances.	ACC	2007	DBLP DOI BibTeX RDF
25	Marco Bergami, Federico Bizzarri, Andrea Carlevaro, Marco Storace	Structurally Stable PWL Approximation of Nonlinear Dynamical Systems Admitting Limit Cycles: An Example.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
25	Enis Günay, Mustafa Alçi	n-Double Scrolls in SC-CNN Circuit via diode-Based PWL Function.	Int. J. Bifurc. Chaos	2006	DBLP DOI BibTeX RDF
25	Lorenzo Repetto, Mauro Parodi, Marco Storace	A procedure for the computation of accurate PWL approximations of non-linear dynamical systems.	Int. J. Circuit Theory Appl.	2006	DBLP DOI BibTeX RDF
25	Dan Sui, Chong Jin Ong	Outer Approximation of the Minimal Disturbance Invariant Set of PWL Systems with Bounded Disturbances.	ICARCV	2006	DBLP DOI BibTeX RDF
25	Junaid M. Khan, Shuning Wang	Automatic cruise control modeling- a lattice PWL approximation approach.	ITSC	2006	DBLP DOI BibTeX RDF
25	Andrea de Bono, Lucio Badiali	PWL 1.0 Personal WaveLab: an object-oriented workbench for seismogram analysis on Windows systems.	Comput. Geosci.	2005	DBLP DOI BibTeX RDF
25	Marco Storace, Mauro Parodi	Towards analog implementations of PWL two-dimensional non-linear functions.	Int. J. Circuit Theory Appl.	2005	DBLP DOI BibTeX RDF
25	Ion Necoara, Bart De Schutter, Ton J. J. van den Boom, Johannes Hellendoorn	Robustly stabilizing MPC for perturbed PWL systems.	CDC/ECC	2005	DBLP DOI BibTeX RDF
25	Mauro Gaggero, Mauro Parodi, Marco Storace	Multiresolution PWL approximations.	ECCTD	2005	DBLP DOI BibTeX RDF
25	Oscar De Feo, Marco Storace	PWL identification of dynamical systems: some examples.	ISCAS (4)	2004	DBLP BibTeX RDF
25	Luigi Fortuna, Alessandro Rizzo, Maria Gabriella Xibilia	Modeling Complex Dynamics via Extended PWL-Based CNNs.	Int. J. Bifurc. Chaos	2003	DBLP DOI BibTeX RDF
25	Marco Storace, Oscar De Feo	PWL approximation of dynamical systems: an example.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
25	Stefano Pastore, Amedeo Premoli	DC analysis of PWL electric networks and sub-networks by means of set theory.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
25	Jerzy J. Dabrowski	Efficient post-layout timing verification via RLC trees and explicit PWL timing integration.	ICECS	2002	DBLP DOI BibTeX RDF
25	Mauro Forti, Luca Pancioni, Santina Rocchi, Valerio Vignoli	Accurate CMOS implementation of PWL CNN neuron activations.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
25	Lluís Alsedà, Miguel Antonio del Río, José Ángel Rodríguez	A Note on the Totally Transitive Graph Maps stability of PWL Cellular.	Int. J. Bifurc. Chaos	2001	DBLP DOI BibTeX RDF
25	Mauro Forti, Alberto Tesi	A New Method to Analyze Complete stability of PWL Cellular Neural Networks.	Int. J. Bifurc. Chaos	2001	DBLP DOI BibTeX RDF
25	Federico Bizzarri, Marco Storace, Laura Gardini, Renzo Lupini	Bifurcation Analysis of a PWL Chaotic Circuit Based on Hysteresis through a One-Dimensional Map.	Int. J. Bifurc. Chaos	2001	DBLP DOI BibTeX RDF
25	Mario Biey, Marco Gilli, Ivan A. Maio, Amedeo Premoli	Fast and accurate analysis of one‐dimensional arrays of dynamic PWL cells.	Int. J. Circuit Theory Appl.	2001	DBLP DOI BibTeX RDF
25	Federico Bizzarri, Marco Storace	2-D bifurcation diagram of an oscillator based on PWL hysteresis.	ISCAS (3)	2001	DBLP DOI BibTeX RDF
25	Pedro Julián, Belén D'Amico, Alfredo C. Desages	A model reduction procedure for high level canonical PWL functions.	ISCAS	2000	DBLP DOI BibTeX RDF
25	Marco Storace, Mauro Parodi	On the representation of static hysteresis curves by a PWL ladder circuit.	Int. J. Circuit Theory Appl.	1998	DBLP DOI BibTeX RDF
25	Nathalie Plaziac, Chon-Tam LeDinh, Jean-Pierre Adoul	PWL nonlinear adaptive filter via RLS and NLMS algorithms.	IEEE Trans. Signal Process.	1997	DBLP DOI BibTeX RDF
25	Wenzhe Li, Ji-Nan Lin, Rolf Unbehauen	On description of impulsive noise removal using PWL filter model.	ICASSP	1997	DBLP DOI BibTeX RDF
25	Mauro Parodi, Marco Storace, Silvano Cincotti	Static and dynamic hysteretic features in a PWL circuit.	Int. J. Circuit Theory Appl.	1996	DBLP DOI BibTeX RDF
25	S. Ahmadi, Louiza Sellami, Robert W. Newcomb	A CMOS PWL Fuzzy Membership Function.	ISCAS	1995	DBLP DOI BibTeX RDF
25	Mauro Parodi, Marco Storace, Silvano Cincotti	A PWL ladder circuit which exhibits hysteresis.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
25	Ji-Nan Lin, Rolf Unbehauen	Canonical PWL network and multilayer perceptron-like networks: A unified view.	ISCAS	1993	DBLP BibTeX RDF
18	Yigang He, Wenji Zhu	Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks and Multi-Space Transformations.	ISNN (3)	2009	DBLP DOI BibTeX RDF	Bilinear Transformation, Space Transformation, Neural Network, Fault Diagnosis, Analog Circuits
18	Vladimir Havel, Karel K. Vlcek	Computation of a nonlinear squashing function in digital neural networks.	DDECS	2008	DBLP DOI BibTeX RDF
18	Pavel Horsky	LC Oscillator Driver for Safety Critical Applications.	DATE	2005	DBLP DOI BibTeX RDF
18	Jie Liu, Junan Lu, Xiaoqun Wu	Dynamical analysis for the compound structure of Chen's system.	ICARCV	2004	DBLP DOI BibTeX RDF
18	Jintae Kim, Jaeseo Lee, Lieven Vandenberghe	Techniques for improving the accuracy of geometric-programming based analog circuit design optimization.	ICCAD	2004	DBLP DOI BibTeX RDF
18	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	Optimal decoupling capacitor sizing and placement for standard-cell layout designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
18	Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram	Symbolic Analysis of Nonlinear Analog Circuits.	DATE	2003	DBLP DOI BibTeX RDF
18	Gianluca Giustolisi, Alessandro Rizzo	CMOS implementation of an extended CNN cell to deal with complex dynamics.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
18	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
18	Premal Buch, Ernest S. Kuh	SYMPHONY: A Fast Mixed Signal Simulator for BiMOS Analog/Digital Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF