Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
99 | G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin |
Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings, pp. 384-398, 2006, Springer, 3-540-46559-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
QDI Asynchronous circuits, Path Swapping (PS), Power analysis |
90 | Recep O. Ozdag, Peter A. Beerel |
High-Speed QDI Asynchronous Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK, pp. 13-22, 2002, IEEE Computer Society, 0-7695-1540-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
conditional split, conditional join, QDI, pipelines, asynchronous, dynamic logic, joins, non-linear, fine-grain, micropipelines, forks |
77 | Wonjin Jang, Alain J. Martin |
SEU-Tolerant QDI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 156-165, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
60 | Mehrdad Najibi, Kamran Saleh, Hossein Pedram |
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 299-304, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, standard-cell layout, asynchronous circuits |
60 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin |
Automatic Generation of 1-of-M QDI Asynchronous Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 149-154, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
52 | Charlie Brej, Doug Edwards |
Forward and backward guarding in early output logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 226-229, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
52 | G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard |
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 11-24, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Hardening Techniques against Transient Faults for Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 129-134, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel |
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 361-364, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Anh-Vu Dinh-Duc |
Synthèse automatique de circuits asynchrones QDI. (Automatic synthesis of QDI asynchronous circuits). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2003 |
RDF |
|
48 | Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky |
An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSD ![In: Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 6-9 June 2005, St. Malo, France, pp. 68-76, 2005, IEEE Computer Society, 0-7695-2363-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
asynchronous EDA, QDI, synthesis, ASIC, HDL |
42 | Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram |
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 463-473, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram |
A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 471-472, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
42 | Eslam Yahya, Marc Renaudin |
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 583-592, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
42 | Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin |
Statistic Implementation of QDI Asynchronous Primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 181-191, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin |
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 55-69, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain |
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 424-429, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Asynchronous circuits transient faults sensitivity evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 863-868, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault |
35 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin |
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 171-180, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Nattha Sretasereekul, Takashi Nanya |
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 437-442, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach |
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 149-158, 2008, IEEE Computer Society, 978-0-7695-3098-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous |
25 | Raghda El Shehaby, Matthias Függer, Andreas Steininger |
On the Susceptibility of QDI Circuits to Transient Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.14106, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Shahzad Haider, Song Chen 0001 |
Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: 66th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2023, Tempe, AZ, USA, August 6-9, 2023, pp. 556-560, 2023, IEEE, 979-8-3503-0210-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Matheus Trevisan Moreira, William Koven, Tony F. Wu, Huseyin Ekin Sumbul, Edith Beigné |
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 28th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2023, Beijing, China, July 16-19, 2023, pp. 58-59, 2023, IEEE, 979-8-3503-0576-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Shahzad Haider, Junhao Liang, Song Chen 0001 |
Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0024-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Shahzad Haider, Ke Hu, Song Chen 0001 |
Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOCC ![In: 36th IEEE International System-on-Chip Conference, SOCC 2023, Santa Clara, CA, USA, September 5-8, 2023, pp. 1-5, 2023, IEEE, 979-8-3503-0011-6. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Raghda El Shehaby, Matthias Függer, Andreas Steininger |
On the Susceptibility of QDI Circuits to Transient Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FORMATS ![In: Formal Modeling and Analysis of Timed Systems - 21st International Conference, FORMATS 2023, Antwerp, Belgium, September 19-21, 2023, Proceedings, pp. 69-85, 2023, Springer, 978-3-031-42625-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Zaheer Tabassam, Andreas Steininger |
Towards Resilient QDI Pipeline Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 25th Euromicro Conference on Digital System Design, DSD 2022, Maspalomas, Spain, August 31 - Sept. 2, 2022, pp. 657-664, 2022, IEEE, 978-1-6654-7404-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Gabriel C. Duarte, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista |
Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 13th IEEE Latin America Symposium on Circuits and System, LASCAS 2022, Puerto Varas, Chile, March 1-4, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-2008-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Rodrigo N. Wuerdig, Marcos L. L. Sartori, Brunno A. Abreu, Sergio Bampi, Ney Laert Vilar Calazans |
Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, pp. 1269-1273, 2022, IEEE, 978-1-6654-8485-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Raghda El Shehaby, Andreas Steininger |
Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5938-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Zaheer Tabassam, Andreas Steininger |
SET Hardened Derivatives of QDI Buffer Template. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-5938-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
25 | Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam |
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021, Beijing, China, September 7-10, 2021, pp. 25-33, 2021, IEEE, 978-1-7281-4132-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista |
A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 12th IEEE Latin America Symposium on Circuits and System, LASCAS 2021, Arequipa, Peru, February 21-24, 2021, pp. 1-4, 2021, IEEE, 978-1-7281-7670-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Qingyun Zou, Xiaoxin Cui, Yi Zhong, Zhenhui Dai, Yisong Kuang |
A fully asynchronous QDI mesh router based on 28nm standard cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Thomas R. Barrick, Catherine A. Spilling, Carson Ingo, Jeremy Madigan, Jeremy D. Isaacs, Philip Rich, Timothy L. Jones, Richard L. Magin, Matt G. Hall, Franklyn A. Howe |
Quasi-diffusion magnetic resonance imaging (QDI): A fast, high b-value diffusion imaging technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NeuroImage ![In: NeuroImage 211, pp. 116606, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Matheus Trevisan Moreira, Stefano Giaconi |
Chronos Link: A QDI Interconnect for Modern SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 26th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2020, Salt Lake City, UT, USA, May 17-20, 2020, pp. 67-68, 2020, IEEE, 978-1-7281-5495-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans |
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 26th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2020, Salt Lake City, UT, USA, May 17-20, 2020, pp. 3-10, 2020, IEEE, 978-1-7281-5495-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Duarte Lopes de Oliveira, Gabriel C. Duarte, Nicolly N. M. Cardoso, Gracieth Cavalcanti Batista |
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 33rd Symposium on Integrated Circuits and Systems Design, SBCCI 2020, Campinas, Brazil, August 24-28, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-9625-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Raghda El Shehaby, Andreas Steininger |
On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 38th IEEE International Conference on Computer Design, ICCD 2020, Hartford, CT, USA, October 18-21, 2020, pp. 441-444, 2020, IEEE, 978-1-7281-9710-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Sergio Bampi, Ney Laert Vilar Calazans |
Leveraging QDI Robustness to Simplify the Design of IoT Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-5, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
25 | Ghania Ait Abdelmalek, Rezki Ziani, Rabah Mokdad |
Security and fault tolerance evaluation of TMR-QDI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Inf. Secur. ![In: IET Inf. Secur. 13(3), pp. 213-222, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Ned Bingham, Rajit Manohar |
QDI Constant-Time Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(1), pp. 83-91, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Jean-Philippe Georges |
Performance evaluation & network automation. For a triptych QoS, QoE, QiS. (Évaluation de performances & automatisation de réseaux. Pour un triptyque QdS, QdE, QdI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2019 |
RDF |
|
25 | Marcos L. L. Sartori, Rodrigo N. Wuerdig, Matheus T. Moreira, Ney Laert Vilar Calazans |
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019, pp. 114-123, 2019, IEEE, 978-1-5386-4747-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
25 | Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang |
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(1), pp. 196-200, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
25 | Kwen-Siong Chong, Weng-Geng Ho, Tong Lin 0001, Bah-Hwee Gwee, Joseph S. Chang |
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 402-415, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel |
Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2), pp. 265-278, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Ricardo A. Guazzelli, Matheus T. Moreira, Ney Laert Vilar Calazans |
A comparison of asynchronous QDI templates using static logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: 8th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2017, Bariloche, Argentina, February 20-23, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-5859-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee |
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
25 | Syed Rafay Hasan, Waqas Gul, Osman Hasan |
Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 52, pp. 367-380, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Benjamin Z. Tang, Frank Lane |
Low Power QDI Asynchronous FFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016, pp. 87-88, 2016, IEEE Computer Society, 978-1-4673-9007-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Weng-Geng Ho, Nan Liu 0002, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang |
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 1762-1765, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Waqas Gul, Syed Rafay Hasan, Osman Hasan, Faiq Khalid Lodhi, Falah R. Awwad |
Synchronously triggered GALS design templates leveraging QDI asynchronous interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, pp. 2615-2618, 2016, IEEE, 978-1-4799-5341-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Weng-Geng Ho, Ali Akbar Pammu, Nan Liu 0002, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee |
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISIC ![In: International Symposium on Integrated Circuits, ISIC 2016, Singapore, December 12-14, 2016, pp. 1-4, 2016, IEEE, 978-1-4673-9019-4. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Sean Keller, Alain J. Martin, Chris Moore |
DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015, pp. 37-44, 2015, IEEE Computer Society, 978-1-4799-8716-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Bo-Yuan Huang 0001, Yi-Hsiang Lai, Jie-Hong Roland Jiang |
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015, pp. 434-441, 2015, IEEE, 978-1-4673-8389-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Fu-Chiung Cheng, An-Hao Peng, Xiao-Li Lin, Shu-Chuan Huang |
Hybrid encoded QDI combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar |
Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2712-2715, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Guangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang 0003 |
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 38(8), pp. 826-842, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7), pp. 989-1002, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Matheus T. Moreira, Ney Laert Vilar Calazans |
Advances on the state of the art in QDI design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014, pp. 163-164, 2014, IEEE, 978-1-4799-6016-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel |
Reconditioning: Automatic Power Optimization of QDI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014, pp. 77-84, 2014, IEEE Computer Society, 978-1-4799-3789-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Fu-Chiung Cheng, Yuan-Feng Chen, Shu-Chuan Huang, Ching-Yang Huang |
Synthesis of QDI FSMs from Synchronous Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014, pp. 61-68, 2014, IEEE Computer Society, 978-1-4799-3789-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho |
Synthesis of asynchronous QDI circuits using synchronous coding specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 153-156, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Matheus Trevisan Moreira, Ricardo Aquino Guazzelli, Guilherme Heck, Ney Laert Vilar Calazans |
Hardening QDI circuits against transient faults using delay-insensitive maxterm synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014, pp. 3-8, 2014, ACM, 978-1-4503-2816-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans |
Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014, pp. 692-699, 2014, IEEE, 978-1-4799-3945-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Masashi Imai, Tomohiro Yoneda |
Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014, Ishigaki, Japan, November 17-20, 2014, pp. 687-690, 2014, IEEE, 978-1-4799-5230-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Guangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang 0003 |
Transient Fault Tolerant QDI Interconnects Using Redundant Check Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013, pp. 3-10, 2013, IEEE Computer Society, 978-1-4799-2978-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Jérémie Hamon, Edith Beigné |
Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, pp. 142-149, 2013, IEEE Computer Society, 978-1-4673-5956-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Fu-Chiung Cheng, Chi Chen |
Can QDI Combinational Circuits be Implemented without C-elements? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013, pp. 134-141, 2013, IEEE Computer Society, 978-1-4673-5956-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang |
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, pp. 353-356, 2013, IEEE, 978-1-4673-5760-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
25 | Yvain Thonnart, Edith Beigné, Pascal Vivet |
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012, pp. 73-80, 2012, IEEE Computer Society, 978-1-4673-1360-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha |
A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012, pp. 25-32, 2012, IEEE Computer Society, 978-1-4673-1360-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Matheus T. Moreira, Ricardo A. Guazzelli, Ney Laert Vilar Calazans |
Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 25th Symposium on Integrated Circuits and Systems Design, SBCCI 2012, Brasilia, Brazil, August 30 - September 2, 2012, pp. 1-6, 2012, IEEE, 978-1-4673-2606-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
25 | Nilanka T. Rajapaksha, Arjuna Madanayake |
Asynchronous-QDI 2D IIR digital filter circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, pp. 665-668, 2011, IEEE, 978-1-4244-9473-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
25 | Werner Friesenbichler, Thomas Panhofer, Andreas Steininger |
A deterministic approach for hardware fault injection in asynchronous QDI logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010, pp. 317-322, 2010, IEEE Computer Society, 978-1-4244-6612-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
25 | Khaled Alsayeg, Katell Morin-Allory, Laurent Fesquet |
RAT-based formal verification of QDI asynchronous controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings, pp. 1-6, 2009, IEEE, 978-2-9530504-1-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP BibTeX RDF |
|
25 | Ali-Asghar Salehpour, Masoud Zamani, Amir-Mohammad Rahmani, Siamak Mohammadi, Hossein Pedram, Mohammadreza Binesh Marvasti |
A novel test environment for template based QDI asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008, pp. 526-529, 2008, IEEE, 978-1-4244-2181-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | J. Fragoso, Gilles Sicard, Marc Renaudin |
Estimation rapide du couple énergie/délai des circuits asynchrones QDI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Tech. Sci. Informatiques ![In: Tech. Sci. Informatiques 26(5), pp. 535-565, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Recep O. Ozdag, Peter A. Beerel |
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(9), pp. 975-985, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Recep O. Ozdag, Peter A. Beerel |
A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 187-197, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin |
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWLS ![In: 11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA., pp. 191-196, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
17 | Werner Friesenbichler, Thomas Panhofer, Martin Delvai |
A comprehensive approach for soft error tolerant Four State Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 214-217, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Gang Jin, Lei Wang 0011, Zhiying Wang |
The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: International Conference on Networking, Architecture, and Storage, NAS 2009, 9-11 July 2009, Zhang Jia Jie, Hunan, China, pp. 357-364, 2009, IEEE Computer Society, 978-0-7695-3741-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Werner Friesenbichler, Thomas Panhofer, Martin Delvai |
Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 267-270, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Behnam Ghavami, Hossein Pedram |
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 330-339, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 113-120, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1104-1115, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks |
17 | Alain J. Martin |
Can Asynchronous Techniques Help the SoC Designer? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 7-11, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach |
A DFT Architecture for Asynchronous Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 219-224, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Yong Xiao, Runde Zhou |
Single-track asynchronous pipeline controller design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 764-768, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar |
Asynchronous gate-diffusion-input (GDI) circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(8), pp. 847-856, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mohammad K. Akbari, Ali Jahanian 0001, Mohsen Naderi, Bahman Javadi |
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France, pp. 611-614, 2004, IEEE Computer Society, 0-7695-2203-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | David Fang, Rajit Manohar |
Non-Uniform Access Asynchronous Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 75-85, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mika Nyström, Elaine Ou, Alain J. Martin |
An Eight-Bit Divider Implemented in Asynchronous Pulse Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 229-239, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Yannick Monnet, Marc Renaudin, Régis Leveugle |
Asynchronous Circuits Sensitivity to Fault Injection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal, pp. 121-128, 2004, IEEE Computer Society, 0-7695-2180-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari |
An Asynchronous Viterbi Decoder for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, pp. 471-480, 2003, Springer, 3-540-20074-6. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Paul I. Pénzes, Alain J. Martin |
An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 640-647, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Marc Renaudin, Pascal Vivet, Frédéric Robin |
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 22-31, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design |