Search results for "RASSP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
157	John Welsh, Bipin Chadha, Biju Kalathil, Peter Holmes, Mary Catherine Tuck, William Selvidge, Elisa Finnie, Lynwood Hines	RASSP Enterprise Technologies for Signal Processor Life-Cycle Support.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
136	James E. Saultz	Rapid Prototyping of Application-Specific Signal Processors (RASSP) In-Progress Report.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
115	Mark A. Richards, Anthony Gadient, Geoffrey A. Frank, Randolph Harr	The RASSP Program: Origin, Concepts, and Status: An Introduction to the Issue.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
115	Geoffrey A. Frank, Bernard Clark, W. Bernard Schaming, William Kline	Hardware/Software Codesign from the RASSP Perspective.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
94	Larry Scanlan, Wing Lee, Mike Vahey, Mike McCollough	RASSP Methodology Evaluation and Lessons Learned Developing IRST Signal Processor.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
73	James H. M. Malley	RASSP: Changing the Paradigm of Electronic-System Design.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
63	J. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf	Developing and Distributing Component-Level VHDL Models.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
52	Richard M. Sedmak, John S. Evans	Spanning the Product Life Cycle: RASSP DFT.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
42	Thomas Egolf, Mark Pettigrew, James Debardelaben, Rahmi Hezar, Shahram Famorzadeh, Anil Kumar Kavipurapu, Moinul H. Khan, Lan-Rong Dung, Kasyapa Balemarthy, Neeraj Desai, Vijay K. Madisetti	VHDL-based rapid system prototyping.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
36	Fred Rose, Todd Carpenter, Sanjaya Kumar, John Shackleton, Todd Steeves Honeywell	A Model for the Coanalysis of Hardware and Software Architectures.	CODES	1996	DBLP DOI BibTeX RDF	RASSP, performance modeling, VHDL, hardware/software codesign
31	Martin Zambaldi, Wolfgang Ecker	Extending the RASSP model for Verification.	FDL	2004	DBLP BibTeX RDF
31	David L. Landis	Using RASSP Modules in a Rapid System Prototyping Class.	MSE	1999	DBLP DOI BibTeX RDF
31	C. Hein, J. Pridgen, W. Kline	RASSP Virtual Prototyping of DSP Systems.	DAC	1997	DBLP DOI BibTeX RDF
31	Mark A. Richards, Randolph Reitmeyer Jr., A. Bard, Gerald T. Michael	RASSP: methods and tools for rapid signal processor development, upgrading and life cycle support.	ICASSP	1995	DBLP DOI BibTeX RDF
31	Jack H. Corley, Vijay K. Madisetti, Mark A. Richards	Introduction to ARPA's RASSP initiative and education/facilitation program.	ICASSP	1995	DBLP DOI BibTeX RDF
31	Eric A. Rundquist Jr.	Virtual prototyping of a synthetic aperture radar processor and RASSP benchmark 1.	RSP	1995	DBLP DOI BibTeX RDF
31	Richard M. Sedmak, John Evans	A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP).	ITC	1995	DBLP DOI BibTeX RDF
31	Mark A. Richards	The Rapid Prototyping of Application Specific Signal Processors (RASSP) program: overview and status.	RSP	1994	DBLP DOI BibTeX RDF
31	Cory S. Myers, Paul D. Fiore, J. P. Letellier	Rapid development of signal processors and the RASSP program.	RSP	1994	DBLP DOI BibTeX RDF
21	Randall S. Janka, Linda M. Wills, Lewis Benton Baumstark Jr.	Virtual Benchmarking and Model Continuity in Prototyping Embedded Multiprocessor Signal Processing Systems.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	model continuity, open-standards middleware, specification and design methodology, Hardware/software codesign
21	W. P. Choi, Lee-Ming Cheng	Modelling the Crypto-Processor from Design to Synthesis.	CHES	1999	DBLP DOI BibTeX RDF
21	Rick Miller	VHDL-based EDA Tool Implementation with Java.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Hardware/Software CoSynthesis, Java, VHDL
21	Fred Rose, John Shackleton, Carl Hein	Performance Modeling of System Architectures.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
21	Jeff Pridmore, Greg Buchanan, Gerry Caracciolo, Janet Wedgwood	Model-Year Architectures for Rapid Prototyping.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
21	Steve Goddard	Analyzing the Real-Time Properties of a Dataflow Execution Paradigm using a Synthetic Aperture Radar Application.	IEEE Real Time Technology and Applications Symposium	1997	DBLP DOI BibTeX RDF