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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 4 keywords
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Results
Found 25 publication records. Showing 25 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
157 | John Welsh, Bipin Chadha, Biju Kalathil, Peter Holmes, Mary Catherine Tuck, William Selvidge, Elisa Finnie, Lynwood Hines |
RASSP Enterprise Technologies for Signal Processor Life-Cycle Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 161-176, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
136 | James E. Saultz |
Rapid Prototyping of Application-Specific Signal Processors (RASSP) In-Progress Report. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 29-47, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
115 | Mark A. Richards, Anthony Gadient, Geoffrey A. Frank, Randolph Harr |
The RASSP Program: Origin, Concepts, and Status: An Introduction to the Issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 7-27, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
115 | Geoffrey A. Frank, Bernard Clark, W. Bernard Schaming, William Kline |
Hardware/Software Codesign from the RASSP Perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 63-81, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
94 | Larry Scanlan, Wing Lee, Mike Vahey, Mike McCollough |
RASSP Methodology Evaluation and Lessons Learned Developing IRST Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 145-160, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
73 | James H. M. Malley |
RASSP: Changing the Paradigm of Electronic-System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(3), pp. 23-31, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
63 | J. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf |
Developing and Distributing Component-Level VHDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 111-126, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
52 | Richard M. Sedmak, John S. Evans |
Spanning the Product Life Cycle: RASSP DFT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(3), pp. 32-42, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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42 | Thomas Egolf, Mark Pettigrew, James Debardelaben, Rahmi Hezar, Shahram Famorzadeh, Anil Kumar Kavipurapu, Moinul H. Khan, Lan-Rong Dung, Kasyapa Balemarthy, Neeraj Desai, Vijay K. Madisetti |
VHDL-based rapid system prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 14(2), pp. 125-156, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
36 | Fred Rose, Todd Carpenter, Sanjaya Kumar, John Shackleton, Todd Steeves Honeywell |
A Model for the Coanalysis of Hardware and Software Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Forth International Workshop on Hardware/Software Codesign, CODES 1996, Pittsburgh, PA, USA, March 18-20, 1996, pp. 94-103, 1996, IEEE Computer Society, 0-8186-7243-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
RASSP, performance modeling, VHDL, hardware/software codesign |
31 | Martin Zambaldi, Wolfgang Ecker |
Extending the RASSP model for Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Forum on specification and Design Languages, FDL 2004, September 14-17, 2004, Lille, France, Proceedings, pp. 536-544, 2004, ECSI. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
31 | David L. Landis |
Using RASSP Modules in a Rapid System Prototyping Class. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 53-54, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
31 | C. Hein, J. Pridgen, W. Kline |
RASSP Virtual Prototyping of DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997., pp. 492-497, 1997, ACM Press, 0-89791-920-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
31 | Mark A. Richards, Randolph Reitmeyer Jr., A. Bard, Gerald T. Michael |
RASSP: methods and tools for rapid signal processor development, upgrading and life cycle support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995, pp. 2829-2832, 1995, IEEE Computer Society, 0-7803-2431-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Jack H. Corley, Vijay K. Madisetti, Mark A. Richards |
Introduction to ARPA's RASSP initiative and education/facilitation program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995, pp. 2695-2698, 1995, IEEE Computer Society, 0-7803-2431-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Eric A. Rundquist Jr. |
Virtual prototyping of a synthetic aperture radar processor and RASSP benchmark 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), Chapel Hill, North Carolina, USA, June 7-9, 1995, pp. 79-87, 1995, IEEE Computer Society, 0-8186-7100-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Richard M. Sedmak, John Evans |
A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1995, Driving Down the Cost of Test, Washington, DC, USA, October 21-25, 1995, pp. 319-327, 1995, IEEE Computer Society, 0-7803-2992-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
31 | Mark A. Richards |
The Rapid Prototyping of Application Specific Signal Processors (RASSP) program: overview and status. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, RSP 1994, Grenoble, France, June 20-23, 1994, pp. 1-6, 1994, IEEE Computer Society, 0-8186-5885-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
31 | Cory S. Myers, Paul D. Fiore, J. P. Letellier |
Rapid development of signal processors and the RASSP program. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RSP ![In: Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, RSP 1994, Grenoble, France, June 20-23, 1994, pp. 82-89, 1994, IEEE Computer Society, 0-8186-5885-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Randall S. Janka, Linda M. Wills, Lewis Benton Baumstark Jr. |
Virtual Benchmarking and Model Continuity in Prototyping Embedded Multiprocessor Signal Processing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 28(9), pp. 832-846, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
model continuity, open-standards middleware, specification and design methodology, Hardware/software codesign |
21 | W. P. Choi, Lee-Ming Cheng |
Modelling the Crypto-Processor from Design to Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems, First International Workshop, CHES'99, Worcester, MA, USA, August 12-13, 1999, Proceedings, pp. 25-36, 1999, Springer, 3-540-66646-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Rick Miller |
VHDL-based EDA Tool Implementation with Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 440-445, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Hardware/Software CoSynthesis, Java, VHDL |
21 | Fred Rose, John Shackleton, Carl Hein |
Performance Modeling of System Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 97-109, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Jeff Pridmore, Greg Buchanan, Gerry Caracciolo, Janet Wedgwood |
Model-Year Architectures for Rapid Prototyping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(1-2), pp. 83-96, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Steve Goddard |
Analyzing the Real-Time Properties of a Dataflow Execution Paradigm using a Synthetic Aperture Radar Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: 3rd IEEE Real-Time Technology and Applications Symposium, RTAS '97, Montreal, Canada, June 9-11, 1997, pp. 60-71, 1997, IEEE Computer Society, 0-8186-8016-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
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