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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 10 keywords
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Results
Found 13 publication records. Showing 13 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
40 | Sumeet Kumar, Aneesh Aggarwal |
Self-checking instructions: reducing instruction redundancy for concurrent error detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 64-73, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures |
40 | Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man |
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 76-81, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, VLIW architectures, VLSI systems |
40 | Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck |
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(6), pp. 672-683, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design |
39 | Ciji Isen, Lizy K. John, Eugene John |
A Tale of Two Processors: Revisiting the RISC-CISC Debate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPEC Benchmark Workshop ![In: Computer Performance Evaluation and Benchmarking, SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings, pp. 57-76, 2009, Springer, 978-3-540-93798-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
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39 | Steve Heath |
Microprocessor architectures and systems - RISC, CISC and DSP processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
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1990 |
RDF |
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39 | Patrick Horster, Dietrich Manstetten, Heidrun Pelzer |
Die RISC-CISC Debatte. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Angew. Inform. ![In: Angew. Inform. 29(7), pp. 273-280, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP BibTeX RDF |
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39 | Robert P. Colwell, Charles Y. Hitchcock III, E. Douglas Jensen |
Peering through the RISC/CISC fog: an outline of research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 11(1), pp. 44-50, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
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26 | Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001 |
A retargetable framework for instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 431-452, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm |
26 | Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz |
PISC: Polymorphic Instruction Set Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 274-286, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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26 | Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt |
An efficient retargetable framework for instruction-set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 13-18, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm |
26 | Ramesh V. Peri, Srinivas Doddapaneni |
Compilers and Tools for Embedded Systems - Introduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 4-7 January, 2000, Maui, Hawaii, USA, 2000, IEEE Computer Society, 0-7695-0493-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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26 | Michael W. Hicks, Jonathan T. Moore, Scott Nettles |
The Measured Cost of Copying Garbage Collection Mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFP ![In: Proceedings of the 1997 ACM SIGPLAN International Conference on Functional Programming (ICFP '97), Amsterdam, The Netherlands, June 9-11, 1997., pp. 292-305, 1997, ACM, 0-89791-918-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
OSCAR |
26 | Jochen Liedtke |
A Short Note on Implementing Thread Exclusiveness and Address Space Locking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGOPS Oper. Syst. Rev. ![In: ACM SIGOPS Oper. Syst. Rev. 28(3), pp. 38-42, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
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