Search results for "RISC/CISC"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
40	Sumeet Kumar, Aneesh Aggarwal	Self-checking instructions: reducing instruction redundancy for concurrent error detection.	PACT	2006	DBLP DOI BibTeX RDF	RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures
40	Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man	Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	RISC/CISC, VLIW architectures, VLSI systems
40	Murali Jayapala, Francisco Barat, Tom Vander Aa, Francky Catthoor, Henk Corporaal, Geert Deconinck	Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	RISC/CISC, low-power design, memory management, real-time and embedded systems, VLIW architectures, memory design
39	Ciji Isen, Lizy K. John, Eugene John	A Tale of Two Processors: Revisiting the RISC-CISC Debate.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF
39	Steve Heath	Microprocessor architectures and systems - RISC, CISC and DSP processors.		1990	RDF
39	Patrick Horster, Dietrich Manstetten, Heidrun Pelzer	Die RISC-CISC Debatte.	Angew. Inform.	1987	DBLP BibTeX RDF
39	Robert P. Colwell, Charles Y. Hitchcock III, E. Douglas Jensen	Peering through the RISC/CISC fog: an outline of research.	SIGARCH Comput. Archit. News	1983	DBLP DOI BibTeX RDF
26	Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001	A retargetable framework for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm
26	Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz	PISC: Polymorphic Instruction Set Computers.	ARC	2006	DBLP DOI BibTeX RDF
26	Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt	An efficient retargetable framework for instruction-set simulation.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm
26	Ramesh V. Peri, Srinivas Doddapaneni	Compilers and Tools for Embedded Systems - Introduction.	HICSS	2000	DBLP DOI BibTeX RDF
26	Michael W. Hicks, Jonathan T. Moore, Scott Nettles	The Measured Cost of Copying Garbage Collection Mechanisms.	ICFP	1997	DBLP DOI BibTeX RDF	OSCAR
26	Jochen Liedtke	A Short Note on Implementing Thread Exclusiveness and Address Space Locking.	ACM SIGOPS Oper. Syst. Rev.	1994	DBLP DOI BibTeX RDF