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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 17 occurrences of 16 keywords
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Results
Found 32 publication records. Showing 32 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
53 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Figures of merit to characterize the importance of on-chip inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 7(4), pp. 442-449, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
53 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Figures of Merit to Characterize the Importance of On-Chip Inductance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 560-565, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
47 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Equivalent Elmore delay for RLC trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1), pp. 83-97, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
42 | Selim G. Akl, Weiguang Yao |
A Parallel Approach Eliminates Measurement Perturbations in RLC Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 35(2), pp. 155-164, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RLC-circuit, parallel computation, measurement, dynamical system, oscillation, perturbation, damping |
41 | Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter |
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 628-633, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Yehea I. Ismail, Eby G. Friedman, José Luis Neves |
Signal waveform characterization in RLC trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 190-193, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu 0001 |
General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 633-638, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Liang Yin, Lei He 0001 |
An efficient analytical model of coupled on-chip RLC interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 385-390, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi |
Practical considerations for passive reduction of RLC circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 214-220, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
25 | Lawrence T. Pillage, Ronald A. Rohrer |
Asymptotic waveform evaluation for timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4), pp. 352-366, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
25 | Zi-Ming Wang 0001, Xudong Zhao 0001, Xiaodi Li, Xianfu Zhang, Rui Mu |
Energy-Based Control for Switched Uncertain Port-Controlled Hamiltonian Systems With Its Application to RLC Circuit Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Syst. ![In: IEEE Trans. Syst. Man Cybern. Syst. 54(1), pp. 107-118, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
25 | Matap Shankar, Swaroop Nandan Bora |
Generalized Ulam-Hyers-Rassias Stability of Solution for the Caputo Fractional Non-instantaneous Impulsive Integro-differential Equation and Its Application to Fractional RLC Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 42(4), pp. 1959-1983, April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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25 | Yao Huang, Yao-Lin Jiang, Kang-Li Xu |
Model Order Reduction of RLC Circuit System Modeled by Port-Hamiltonian Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(3), pp. 1542-1546, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
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25 | Issam El Hamdi, Alessandro N. Vargas, Hassane Bouzahir, Ricardo C. L. F. Oliveira, Leonardo Acho |
Robust stability of stochastic systems with varying delays: Application to RLC circuit with intermittent closed-loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Math. Comput. ![In: Appl. Math. Comput. 411, pp. 126541, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
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25 | Kristian Haska, Dusan Zorica, Stevan M. Cveticanin |
Fractional RLC circuit in transient and steady state regimes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. Nonlinear Sci. Numer. Simul. ![In: Commun. Nonlinear Sci. Numer. Simul. 96, pp. 105670, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Krzysztof Oprzedkiewicz |
A Discrete, Fractional Order, Memory-Effective State Space Model of a RLC Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AUTOMATION ![In: Automation 2021: Recent Achievements in Automation, Robotics and Measurement Techniques, September 23-24, 2021, Warsaw, Poland, pp. 46-57, 2021, Springer, 978-3-030-74892-0. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
25 | Ling Zhou, Zhi-zhong Tan, Qing-hua Zhang |
A fractional-order multifunctional n-step honeycomb RLC circuit network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Inf. Technol. Electron. Eng. ![In: Frontiers Inf. Technol. Electron. Eng. 18(8), pp. 1186-1196, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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25 | José Francisco Gómez-Aguilar, Victor Fabian Morales-Delgado, Marco Antonio Taneco-Hernández, Dumitru Baleanu, Ricardo Fabricio Escobar-Jiménez, Maysaa Mohamed Al Qurashi |
Analytical Solutions of the Electrical RLC Circuit via Liouville-Caputo Operators with Local and Non-Local Kernels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Entropy ![In: Entropy 18(8), pp. 402, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
25 | Rui Zhou 0011, Diyi Chen, Herbert H. C. Iu |
Fractional-Order 2 × n RLC Circuit Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(9), pp. 1550142:1-1550142:25, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
25 | Dukgwon Lee, Seunghyun Beak, Youngmin Lee, Eunser Lee, Jungkook Kim, Gyung-Leen Park, Taikyeong Jeong |
Minimize the delay of parasitic capacitance and modeling in RLC circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 614-620, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Elmore, parasitic capacitance, delay, interconnection, oscillator |
25 | Tadashi Kawai, Yasuaki Nakashima, Yoshihiro Kokubo, Isao Ohta |
Dual-Band Wilkinson Power Dividers Using a Series RLC Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(11), pp. 1793-1797, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Yuichi Tanji, Takayuki Watanabe, Hidemasa Kubota, Hideki Asai |
Large scale RLC circuit analysis using RLCG-MNA formulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 45-46, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Aziz S. Inan, Peter M. Osterberg |
Special singularity integrals encountered in electric circuits [RLC circuit examples]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 976-979, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Roland W. Freund, Peter Feldmann |
Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 530-537, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
linear passive multi-terminal circuit, matrix-Pade approximants, Lanczos-type process, interconnect analysis, simulation, synthesis, transfer function |
22 | Nahi H. Abdul Ghani, Farid N. Najm |
Handling inductance in early power grid verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 127-134, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Taeyong Je, Yungseon Eo |
Efficient Signal Integrity Verification Method of Multi-Coupled RLC Interconnect Lines with Asynchronous Circuit Switching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 419-424, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Saed G. Younis, Thomas F. Knight Jr. |
Non-dissipative rail drivers for adiabatic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 404-414, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics |
16 | Tak K. Tang, Michel S. Nakhla |
Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3), pp. 341-352, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
14 | Federico Fontana, Federico Avanzini |
Computation of Delay-Free Nonlinear Digital Filter Networks: Application to Chaotic Circuits and Intracellular Signal Transduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(10-1), pp. 4703-4715, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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14 | Hideo Nakano, Hirohiko Honda, Hideaki Okazaki |
Canards in a slow-fast continuous piecewise linear vector field. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3757-3760, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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14 | Kevin M. Lepak, Min Xu, Jun Chen 0008, Lei He 0001 |
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(3), pp. 290-309, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI physical design automation and on-chip inductance, net ordering, noise minimization, signal integrity, shielding |
14 | Guoan Zhong, Cheng-Kok Koh, Kaushik Roy 0001 |
On-chip interconnect modeling by wire duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 341-346, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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