Search results for "RapidIO"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
174	David Bueno, Adam Leko, Chris Conger, Ian A. Troxel, Alan D. George	Simulative Analysis of the RapidIO Embedded Interconnect Architecture for Real-Time, Network-Intensive Applications.	LCN	2004	DBLP DOI BibTeX RDF	RapidIO, space-based radar, ground-moving target indicator, embedded signal processing
129	David Bueno, Chris Conger, Alan D. George, Ian A. Troxel, Adam Leko	RapidIO for radar processing in advanced space systems.	ACM Trans. Embed. Comput. Syst.	2007	DBLP DOI BibTeX RDF	RapidIO, ground-moving target indicator, space-based radar, synthetic aperture radar
84	Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt	Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities.	VTS	2005	DBLP DOI BibTeX RDF	RapidIO, Source-Synchronous, LVDS, Differential, ATE, Non-determinism
76	Jonathan Adams, Constantine Katsinis, Warren Rosen, Diana Hecht, Vaughn Adams, Harsha Narravula, Satyen Sukhtankar	Simulation Experiments of a High-Performance RapidIO-based Processing Architecture.	NCA	2001	DBLP DOI BibTeX RDF
45	Michael Jones, Aaron Benson, Dan Delorey	Proving Compatibility Using Refinement.	TPHOLs	2004	DBLP DOI BibTeX RDF
31	Yanming Fu, Youquan Jia, Baohua Huang, Xing Zhou, Xiaoqiong Qin	The RapidIO Routing Strategy Based on the Double-Antibody Group Multi-Objective Artificial Immunity Algorithm.	Sensors	2022	DBLP DOI BibTeX RDF
31	N. I. V'yukova, V. A. Galatenko, A. N. Pavlov, S. V. Samborskii	Mapping Parallel Computations to Distributed Systems Based on RapidIO Technology.	Program. Comput. Softw.	2020	DBLP DOI BibTeX RDF
31	Xuwen Li, Jiashun Hu, Xuegang Wu, Qiang Wu	Software Design of Hardware-in-the-loop Simulation System Based on RapidIO.	ICCPR	2019	DBLP DOI BibTeX RDF
31	Chunmei Hu, Zhenyang Zhang, Yang Guo, Jingyan Xu	A Implementation for Built-in Self-Testing of RapidIO by JTAG.	ASICON	2019	DBLP DOI BibTeX RDF
31	Arun J. Thomas, K. V. Sachin, T. V. Sagar, G. Pradeep, S. V. Hari Prasad, M. Soundarakumar, Vipin Tyagi	A RapidIO-Ethernet System Architecture for TDM-based Satellite Receiver.	CITS	2018	DBLP DOI BibTeX RDF
31	Lin Shu, Jie Hao, Yafang Song, Chengcheng Li, Donglin Wang	Optimal many-to-many personalized concurrent communication in RapidIO-based fat-trees.	SNPD	2016	DBLP DOI BibTeX RDF
31	Abdessamad Klilou, Said Belkouch, Philippe Elleaume, Philippe Le Gall, François Bourzeix, Moha M'rabet Hassani	Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect.	EURASIP J. Adv. Signal Process.	2014	DBLP DOI BibTeX RDF
31	Fengfeng Wu, Song Jia, Qinglong Meng, Shigong Lv, Yuan Wang 0001, Dacheng Zhang	Improved CRC Calculation Strategies for 64-bit Serial RapidIO.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
31	Zhan Xu, Xiao Wu, Yi Wu	A New System Interconnection Architecture Based on RapidIO Using Partial Reconfiguration.	DASC	2013	DBLP DOI BibTeX RDF
31	Moritz Schmid, Frank Hannig, Jürgen Teich	Power Management Strategies for Serial RapidIO Endpoints in FPGAs.	FCCM	2012	DBLP DOI BibTeX RDF
31	David Bueno, Chris Conger, Alan D. George	Optimizing rapidIO architectures for onboard processing.	ACM Trans. Embed. Comput. Syst.	2010	DBLP DOI BibTeX RDF
31	Jiansheng Xing, Bart D. Theelen, Rom Langerak, Jaco van de Pol, Jan Tretmans, Jeroen Voeten	UPPAAL in Practice: Quantitative Verification of a RapidIO Network.	ISoLA (2)	2010	DBLP DOI BibTeX RDF
31	Syed Ijlal Ali Shah, Shashank Khanvilkar, Ashfaq A. Khokhar	RapidIO traffic management and flow arbitration protocol.	IEEE Commun. Mag.	2006	DBLP DOI BibTeX RDF
31	Christian Sauer 0001, Matthias Gries, José Ignacio Gómez, Scott J. Weber, Kurt Keutzer	Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express.	PARELEC	2004	DBLP DOI BibTeX RDF
31	Martin McKenny, Julian A. B. Dines, David Harle	Transporting multiple classes of traffic over a generic routing device - an investigation into the performance of the RapidIO™ interconnect architecture.	ICON	2003	DBLP DOI BibTeX RDF
23	Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei	A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis
23	Graham Schelle, Dirk Grunwald	CUSP: a modular framework for high speed network applications on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	networking, parallelism, reconfigurable hardware, speculation
23	Satyen Sukhtankar, Diana Hecht, Warren Rosen	A Novel Switch Architecture for High-Performance Computing and Signal Processing Networks.	NCA	2004	DBLP DOI BibTeX RDF
23	Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow	Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions.	ITC	2004	DBLP DOI BibTeX RDF
23	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov	Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis