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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 31 occurrences of 31 keywords
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Results
Found 50 publication records. Showing 50 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
188 | Biwei Liu, Shuming Chen, Hu Xiao |
Analysis of Glitch Reconvergence in Combinational Logic SER Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: Second Asia International Conference on Modelling and Simulation, AMS 2008, Kuala Lumpur, Malaysia, May 13-15, 2008, pp. 1015-1020, 2008, IEEE Computer Society, 978-0-7695-3136-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Reconvergence, SER esitmation, SET |
121 | Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003 |
Control Flow Optimization Via Dynamic Reconvergence Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 129-140, 2004, IEEE Computer Society, 0-7695-2126-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
66 | Shiy Xu, E. Edirisuriya |
A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 354-357, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Fanout branch, Reconvergence, Testability, Testable Design, Fanout |
66 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Statistical timing analysis with path reconvergence and spatial correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 528-532, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
66 | Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma |
Crosstalk analysis using reconvergence correlation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 79-83, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
48 | Jindrich Zejda, Paul Frain |
General framework for removal of clock network pessimism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 632-639, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron |
48 | Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen |
Identification of robust untestable path delay faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 229-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification |
47 | A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001 |
SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 251, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001 |
Synthesis of skewed logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(2), pp. 205-228, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Skewed logic, optimization, synthesis, power |
37 | R. Manimegalai, A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001 |
MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1185, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen |
Single-fault fault-collapsing analysis in sequential logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12), pp. 1559-1568, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
29 | Haibo Ge, Guanlong Meng, Bofeng Li |
Zero-Reconvergence PPP for Real-Time Low-Earth Satellite Orbit Determination in Case of Data Interruption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. ![In: IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 17, pp. 4705-4715, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
29 | Liwei Ni, Zonglin Yang, Jiaxi Zhang 0001, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li |
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2312.14536, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Liwei Ni, Zonglin Yang, Jiaxi Zhang 0001, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li |
Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 41st IEEE International Conference on Computer Design, ICCD 2023, Washington, DC, USA, November 6-8, 2023, pp. 336-343, 2023, IEEE, 979-8-3503-4291-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli |
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, Taipei, Taiwan, January 17-20, 2022, pp. 395-402, 2022, IEEE, 978-1-6654-2135-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Juan Brenes, Alberto García-Martínez, Marcelo Bagnulo, Andra Lutu, Cristel Pelsser |
Power Prefixes Prioritization for Smarter BGP Reconvergence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 28(3), pp. 1074-1087, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Sana Damani, Daniel R. Johnson, Mark Stephenson, Stephen W. Keckler, Eddie Q. Yan, Michael McKeown, Olivier Giroux |
Speculative reconvergence for improved SIMT efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, San Diego, CA, USA, February, 2020, pp. 121-132, 2020, ACM, 978-1-4503-7047-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Lujie Zhang, Chang Liu 0019, Long Zhang 0004, Yang Guo 0003 |
一种基于SAT求解器的组合电路重汇聚现象分析方法 (Reconvergence Phenomena Analysis Method in Combinational Circuits Based on SAT Solver). ![Search on Bibsonomy](Pics/bibsonomy.png) |
计算机科学 ![In: 计算机科学 46(4), pp. 309-314, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang |
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2019, Cluj-Napoca, Romania, April 24-26, 2019, pp. 1-2, 2019, IEEE, 978-1-7281-0073-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Irena Seremet, Samir Causevic |
An analysis of reconvergence delay when using BGP-LS/PCEP as southbound protocols. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIPRO ![In: 42nd International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2019, Opatija, Croatia, May 20-24, 2019, pp. 415-420, 2019, IEEE, 978-953-233-098-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Chang Liu 0019, Long Zhang 0004, Xu He, Yang Guo 0003 |
Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 48740-48746, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo |
CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 60, pp. 185-195, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu 0001 |
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 176-181, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
29 | Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo |
Cylindrical Reconvergence Physical Unclonable Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016, pp. 446-453, 2016, IEEE Computer Society, 978-1-5090-2817-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
29 | Walid J. Ghandour, Nadine J. Ghandour |
Position Paper: Leveraging Strength-Based Dynamic Slicing to Identify Control Reconvergence Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014, pp. 1368-1373, 2014, IEEE Computer Society, 978-0-7695-5208-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Nicolas Brunie, Caroline Collange |
Reconvergence de contrôle implicite pour les architectures SIMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Tech. Sci. Informatiques ![In: Tech. Sci. Informatiques 32(2), pp. 153-178, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Samuel N. Pagliarini, Tian Ban, Lirida A. B. Naviner, Jean-François Naviner |
Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013, Columbus, OH, USA, August 4-7, 2013, pp. 113-116, 2013, IEEE. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Qingyu Liu, Yuchun Ma, Yu Wang 0002, Wayne Luk, Jinian Bian |
RALP: Reconvergence-aware layer partitioning for 3D FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico, December 9-11, 2013, pp. 1-6, 2013, IEEE, 978-1-4799-2079-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
29 | Bart Puype, Dimitri Papadimitriou, Goutam Das, Didier Colle, Mario Pickavet, Piet Demeester |
OSPF failure reconvergence through SRG inference and prediction of link state advertisements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCOMM ![In: Proceedings of the ACM SIGCOMM 2011 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications, Toronto, ON, Canada, August 15-19, 2011, pp. 468-469, 2011, ACM, 978-1-4503-0797-0. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
29 | Bart Puype, Dimitri Papadimitriou, Goutam Das, Didier Colle, Mario Pickavet, Piet Demeester |
SRLG Inference in OSPF for Improved Reconvergence after Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ServiceWave ![In: Towards a Service-Based Internet - Third European Conference, ServiceWave 2010, Ghent, Belgium, December 13-15, 2010. Proceedings, pp. 233-234, 2010, Springer, 978-3-642-17693-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
29 | Yinlei Yu, Cameron Brien, Sharad Malik |
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 461-468, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | A. Manoj Kumar, Jayaram Bobba, V. Kamakoti 0001 |
MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 922-929, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | R. Manimegalai, B. Jayaram 0002, A. Manoj Kumar, V. Kamakoti 0001 |
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004, pp. 57-64, 2004, IEEE. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone, Matthew I. Frank |
Exploiting Postdominance for Speculative Parallelization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 295-305, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak |
Statistical timing analysis using Kernel smoothing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 97-102, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
18 | Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen |
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 1183-1191, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Milos Hrkic, John Lillis, Giancarlo Beraudo |
An Approach to Placement-Coupled Logic Replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2539-2551, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Hosung (Leo) Kim, John Lillis, Milos Hrkic |
Techniques for improved placement-coupled logic replication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 211-216, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
placement, timing optimization, programmable logic, logic replication |
18 | Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen |
Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 952-957, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
18 | Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen |
Block based statistical timing analysis with extended canonical timing model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 250-253, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Min Pan, Chris C. N. Chu, Hai Zhou 0001 |
Timing yield estimation using statistical static timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2461-2464, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 58-63, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Gianluca Iannaccone, Chen-Nee Chuah, Richard Mortier, Supratik Bhattacharyya, Christophe Diot |
Analysis of link failures in an IP backbone. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Internet Measurement Workshop ![In: Proceedings of the 2nd ACM SIGCOMM Internet Measurement Workshop, IMW 2002, Marseille, France, November 6-8, 2002, pp. 237-242, 2002, ACM, 1-58113-603-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
IP |
18 | Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk |
Computing observability don't cares efficiently through polarization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7), pp. 573-581, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
18 | Yiorgos Makris, Alex Orailoglu |
RTL Test Justification and Propagation Analysis for Modular Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(2), pp. 105-120, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
RTL testability analysis, test justification, test propagation, DFT, modular design |
18 | José Monteiro 0001, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White 0001 |
Estimation of average switching activity in combinational logic circuits using symbolic simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1), pp. 121-127, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Hoon Choi, Seung Ho Hwang |
Improving the accuracy of support-set finding method for power estimation of combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ED&TC ![In: European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, pp. 526-530, 1997, IEEE Computer Society, 0-8186-7786-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
18 | Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton |
Approximate timing analysis of combinational circuits under the XBD0 model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 176-181, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
delay computation, timing analysis, False path |
18 | Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth |
Fast Power Estimation of Large Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 13(1), pp. 70-78, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
18 | Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk |
Polarized observability don't cares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 626-631, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
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