Search results for "Reconvergence"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
188	Biwei Liu, Shuming Chen, Hu Xiao	Analysis of Glitch Reconvergence in Combinational Logic SER Estimation.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	Reconvergence, SER esitmation, SET
121	Jamison D. Collins, Dean M. Tullsen, Hong Wang 0003	Control Flow Optimization Via Dynamic Reconvergence Prediction.	MICRO	2004	DBLP DOI BibTeX RDF
66	Shiy Xu, E. Edirisuriya	A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	Fanout branch, Reconvergence, Testability, Testable Design, Fanout
66	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Statistical timing analysis with path reconvergence and spatial correlations.	DATE	2006	DBLP DOI BibTeX RDF
66	Sachin Shrivastava, Rajendra Pratap, Harindranath Parameswaran, Manuj Verma	Crosstalk analysis using reconvergence correlation.	ASP-DAC	2006	DBLP DOI BibTeX RDF
48	Jindrich Zejda, Paul Frain	General framework for removal of clock network pessimism.	ICCAD	2002	DBLP DOI BibTeX RDF	clock network reconvergence, voltage and temperature delay variation, process, static timing analysis, deep sub-micron
48	Wen Ching Wu, Chung-Len Lee 0001, Jwu E. Chen	Identification of robust untestable path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	robust untestable path delay faults, path reconvergence of fanouts, ISCAS 85' circuits, total path delay faults, six-valued logic, propagation graph, ROUNTEST program, fault diagnosis, logic testing, delays, partitioning, ATPG, combinational circuits, combinational circuits, automatic testing, logic CAD, multivalued logic, logic partitioning, signal flow graphs, fault identification
47	A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF
37	Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy 0001	Synthesis of skewed logic circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Skewed logic, optimization, synthesis, power
37	R. Manimegalai, A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.	FPL	2004	DBLP DOI BibTeX RDF
37	Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen	Single-fault fault-collapsing analysis in sequential logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
29	Haibo Ge, Guanlong Meng, Bofeng Li	Zero-Reconvergence PPP for Real-Time Low-Earth Satellite Orbit Determination in Case of Data Interruption.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2024	DBLP DOI BibTeX RDF
29	Liwei Ni, Zonglin Yang, Jiaxi Zhang 0001, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li	Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning.	CoRR	2023	DBLP DOI BibTeX RDF
29	Liwei Ni, Zonglin Yang, Jiaxi Zhang 0001, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li	Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning.	ICCD	2023	DBLP DOI BibTeX RDF
29	Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli	Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.	ASP-DAC	2022	DBLP DOI BibTeX RDF
29	Juan Brenes, Alberto García-Martínez, Marcelo Bagnulo, Andra Lutu, Cristel Pelsser	Power Prefixes Prioritization for Smarter BGP Reconvergence.	IEEE/ACM Trans. Netw.	2020	DBLP DOI BibTeX RDF
29	Sana Damani, Daniel R. Johnson, Mark Stephenson, Stephen W. Keckler, Eddie Q. Yan, Michael McKeown, Olivier Giroux	Speculative reconvergence for improved SIMT efficiency.	CGO	2020	DBLP DOI BibTeX RDF
29	Lujie Zhang, Chang Liu 0019, Long Zhang 0004, Yang Guo 0003	一种基于SAT求解器的组合电路重汇聚现象分析方法 (Reconvergence Phenomena Analysis Method in Combinational Circuits Based on SAT Solver).	计算机科学	2019	DBLP DOI BibTeX RDF
29	Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang	Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime.	DDECS	2019	DBLP DOI BibTeX RDF
29	Irena Seremet, Samir Causevic	An analysis of reconvergence delay when using BGP-LS/PCEP as southbound protocols.	MIPRO	2019	DBLP DOI BibTeX RDF
29	Chang Liu 0019, Long Zhang 0004, Xu He, Yang Guo 0003	Analysis of SET Reconvergence and Hardening in the Combinational Circuit Using a SAT-Based Method.	IEEE Access	2018	DBLP DOI BibTeX RDF
29	Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo	CRPUF: A modeling-resistant delay PUF based on cylindrical reconvergence.	Microprocess. Microsystems	2018	DBLP DOI BibTeX RDF
29	Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu 0001	Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs.	ISVLSI	2016	DBLP DOI BibTeX RDF
29	Rodrigo C. Surita, Mario Lúcio Côrtes, Diego F. Aranha, Guido Araujo	Cylindrical Reconvergence Physical Unclonable Function.	DSD	2016	DBLP DOI BibTeX RDF
29	Walid J. Ghandour, Nadine J. Ghandour	Position Paper: Leveraging Strength-Based Dynamic Slicing to Identify Control Reconvergence Instructions.	IPDPS Workshops	2014	DBLP DOI BibTeX RDF
29	Nicolas Brunie, Caroline Collange	Reconvergence de contrôle implicite pour les architectures SIMT.	Tech. Sci. Informatiques	2013	DBLP DOI BibTeX RDF
29	Samuel N. Pagliarini, Tian Ban, Lirida A. B. Naviner, Jean-François Naviner	Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis.	MWSCAS	2013	DBLP DOI BibTeX RDF
29	Qingyu Liu, Yuchun Ma, Yu Wang 0002, Wayne Luk, Jinian Bian	RALP: Reconvergence-aware layer partitioning for 3D FPGAs.	ReConFig	2013	DBLP DOI BibTeX RDF
29	Bart Puype, Dimitri Papadimitriou, Goutam Das, Didier Colle, Mario Pickavet, Piet Demeester	OSPF failure reconvergence through SRG inference and prediction of link state advertisements.	SIGCOMM	2011	DBLP DOI BibTeX RDF
29	Bart Puype, Dimitri Papadimitriou, Goutam Das, Didier Colle, Mario Pickavet, Piet Demeester	SRLG Inference in OSPF for Improved Reconvergence after Failures.	ServiceWave	2010	DBLP DOI BibTeX RDF
29	Yinlei Yu, Cameron Brien, Sharad Malik	Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.	VLSI Design	2008	DBLP DOI BibTeX RDF
29	A. Manoj Kumar, Jayaram Bobba, V. Kamakoti 0001	MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis.	DATE	2004	DBLP DOI BibTeX RDF
29	R. Manimegalai, B. Jayaram 0002, A. Manoj Kumar, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis.	FPT	2004	DBLP DOI BibTeX RDF
18	Mayank Agarwal, Kshitiz Malik, Kevin M. Woley, Sam S. Stone, Matthew I. Frank	Exploiting Postdominance for Speculative Parallelization.	HPCA	2007	DBLP DOI BibTeX RDF
18	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava 0001, Miodrag Potkonjak	Statistical timing analysis using Kernel smoothing.	ICCD	2007	DBLP DOI BibTeX RDF
18	Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen	Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Milos Hrkic, John Lillis, Giancarlo Beraudo	An Approach to Placement-Coupled Logic Replication.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
18	Hosung (Leo) Kim, John Lillis, Milos Hrkic	Techniques for improved placement-coupled logic replication.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	placement, timing optimization, programmable logic, logic replication
18	Lizheng Zhang, Weijen Chen, Yuhen Hu, Charlie Chung-Ping Chen	Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model.	DATE	2005	DBLP DOI BibTeX RDF
18	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Block based statistical timing analysis with extended canonical timing model.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Min Pan, Chris C. N. Chu, Hai Zhou 0001	Timing yield estimation using statistical static timing analysis.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
18	Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara	Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
18	Gianluca Iannaccone, Chen-Nee Chuah, Richard Mortier, Supratik Bhattacharyya, Christophe Diot	Analysis of link failures in an IP backbone.	Internet Measurement Workshop	2002	DBLP DOI BibTeX RDF	IP
18	Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk	Computing observability don't cares efficiently through polarization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
18	Yiorgos Makris, Alex Orailoglu	RTL Test Justification and Propagation Analysis for Modular Designs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	RTL testability analysis, test justification, test propagation, DFT, modular design
18	José Monteiro 0001, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White 0001	Estimation of average switching activity in combinational logic circuits using symbolic simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
18	Hoon Choi, Seung Ho Hwang	Improving the accuracy of support-set finding method for power estimation of combinational circuits.	ED&TC	1997	DBLP DOI BibTeX RDF
18	Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton	Approximate timing analysis of combinational circuits under the XBD0 model.	ICCAD	1997	DBLP DOI BibTeX RDF	delay computation, timing analysis, False path
18	Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth	Fast Power Estimation of Large Circuits.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF
18	Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk	Polarized observability don't cares.	ICCAD	1996	DBLP DOI BibTeX RDF