Search results for "SEMATECH"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	C.-P. Lin, Mu-Der Jeng	An Expanded SEMATECH CIM Framework for Heterogeneous Applications Integration.	IEEE Trans. Syst. Man Cybern. Part A	2006	DBLP DOI BibTeX RDF
67	Wonjae L. Kang, Brad Potts, Ray Hokinson, John Riley, David Doman, Frank Cano, N. S. Nagaraj, Noel Durrant	Enabling DIR(Designing-In-Reliability) through CAD Capabilities.	ISQED	2000	DBLP DOI BibTeX RDF	SEMATECH, design-in-reliability, reliability, Design tools
51	Phil Nigh, David P. Vallett, Atul Patel, Jason Wright	Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.	ITC	1998	DBLP DOI BibTeX RDF
48	B. Chester Hwang	Trends of Key Advanced Device Technologies.	ARVLSI	1997	DBLP DOI BibTeX RDF	SIA roadmap, Sematech, TFSOI, graded-channel CMOS, complementary IC technology, 0.25 micron, CMOS integrated circuits, CMOS technology, Moore's law, GaAs, Si
38	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
38	Shengli Li, Kai Zhang, Jien-Chung Lo	The 2nd Order Analysis of IDDQ Test Data.	DFT	2000	DBLP DOI BibTeX RDF
38	Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana	Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICs.	VTS	2000	DBLP DOI BibTeX RDF
38	S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, Amrich Chokhavtia	CHDStd - application support for reusable hierarchical interconnect timing views.	ISPD	1998	DBLP DOI BibTeX RDF
38	Herb Krasner, Gregory Scott	Lessons Learned from an Initiative for Improving Software Process, Quality, and Reliability in a Semiconductor Equipment Company.	HICSS (1)	1996	DBLP DOI BibTeX RDF
32	Paul Kirsch	Memory overview and RRAM materials development at SEMATECH.	Hot Chips Symposium	2010	DBLP DOI BibTeX RDF
32	Elias G. Carayannis, Jeffrey Alexander	Correction to "Strategy, Structure, and Performance Issues of Precompetitive R&D Consortia: Insights and Lessons Learned From SEMATECH".	IEEE Trans. Engineering Management	2004	DBLP DOI BibTeX RDF
32	Elias G. Carayannis, Jeffrey Alexander	Strategy, structure, and performance issues of precompetitive R&D consortia: insights and lessons learned from SEMATECH.	IEEE Trans. Engineering Management	2004	DBLP DOI BibTeX RDF
32	Seok-Bum Ko, Yu-Yau Guo, Jien-Chung Lo	Studies of the SEMATECH IDDq test data.	J. Syst. Archit.	2002	DBLP DOI BibTeX RDF
32	Peter T. Whelan	Experiences and issues with SEMATECH's CIM framework.	ACM Comput. Surv.	2000	DBLP DOI BibTeX RDF	manufacturing execution system, framework, software component, computer integrated manufacturing
32	Phil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato O. Forlenza, Ray Kurtulik, Wendy Chong	Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.	ITC	1999	DBLP DOI BibTeX RDF
32	Kenneth M. Butler	A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data.	ITC	1999	DBLP DOI BibTeX RDF
32	S. DasGupta	Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel).	ISPD	1998	DBLP DOI BibTeX RDF
32	Adit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh	Binning for IC Quality: Experimental Studies on the SEMATECH Data.	DFT	1998	DBLP DOI BibTeX RDF
32	David Doscher, Robert Hodges	SEMATECH's Experiences with the CIM Framework.	Commun. ACM	1997	DBLP DOI BibTeX RDF
32	Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly	So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.	ITC	1997	DBLP DOI BibTeX RDF
29	Ye Zhang, Wentong Cai 0001, Stephen John Turner	A parallel object-oriented manufacturing simulation language.	Workshop on Parallel and Distributed Simulation	2001	DBLP DOI BibTeX RDF	PARSEC, POMSim, Sematech Data Modeling Standard, parallel simulation languages, semiconductor manufacturing, object-oriented simulation
29	Stephen John Turner, Wentong Cai 0001, Boon-Ping Gan	Adapting a Supply-Chain Simulation for HLA.	DS-RT	2000	DBLP DOI BibTeX RDF	Supply-chain Simulation, Sematech Modeling Data Standard (MDS), High Level Architecture (HLA), Run-Time Infrastructure (RTI), Semiconductor Manufacturing
19	Ralph Mueller, Christos Alexopoulos, Leon F. McGinnis	Automatic generation of simulation models for semiconductor manufacturing.	WSC	2007	DBLP DOI BibTeX RDF
19	Alberto L. Sangiovanni-Vincentelli	The Tides of EDA.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
19	Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal	New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss.	VLSI Design	2003	DBLP DOI BibTeX RDF
19	Sagar S. Sabade, D. M. H. Walker	Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification.	VLSI Design	2003	DBLP DOI BibTeX RDF	spatial correlation, IDDQ testing, delta IDDQ
19	Chao Qi, Tuck Keat Tang, Appa Iyer Sivakumar	Modeling methodology: simulation based cause and effect analysis of cycle time and WIP in semiconductor wafer fabrication.	WSC	2002	DBLP DOI BibTeX RDF
19	Sagar S. Sabade, D. M. H. Walker	Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.	DFT	2002	DBLP DOI BibTeX RDF
19	Sagar S. Sabade, D. M. H. Walker	Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction.	VTS	2002	DBLP DOI BibTeX RDF
19	David I. Bergman, Hans Engler	Improved IDDQ Testing with Empirical Linear Prediction.	ITC	2002	DBLP DOI BibTeX RDF
19	Hailong Cui, Sharad C. Seth, Shashank K. Mehta	A Novel Method to Improve the Test Efficiency of VLSI Tests.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
19	Sagar S. Sabade, D. M. H. Walker	Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
19	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model.	VTS	2001	DBLP DOI BibTeX RDF
19	Claude Thibeault	On the Comparison of IDDQ and IDDQ Testing.	VTS	1999	DBLP DOI BibTeX RDF
19	Claude Thibeault	Increasing Current Testing Resolution.	DFT	1998	DBLP DOI BibTeX RDF	current signatures, test, Integrated circuits, Iddq testing
19	Claude Thibeault, Luc Boisvert	Diagnosis method based on ΔIddq probabilistic signatures: experimental results.	ITC	1998	DBLP DOI BibTeX RDF
19	Anne E. Gattiker, Wojciech Maly	Toward understanding "Iddq-only" fails.	ITC	1998	DBLP DOI BibTeX RDF
19	Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken	An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing.	VTS	1997	DBLP DOI BibTeX RDF	semiconductor testing, stuck-fault testing, ASIC device, application specific integrated circuits, functional testing, IDDQ testing, delay-fault testing, scan testing
19	Jerry M. Soden, Charles F. Hawkins	IDDQ Testing: Issues Present and Future.	IEEE Des. Test Comput.	1996	DBLP DOI BibTeX RDF