Search results for "SPEC95"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
42	Matthew A. Postiff, David A. Greene, Gary S. Tyson, Trevor N. Mudge	The limits of instruction level parallelism in SPEC95 applications.	SIGARCH Comput. Archit. News	1999	DBLP DOI BibTeX RDF
42	Mark J. Charney, Thomas R. Puzak	Prefetching and memory system behavior of the SPEC95 benchmark suite.	IBM J. Res. Dev.	1997	DBLP DOI BibTeX RDF
42	Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad	Execution Characteristics of Desktop Applications on Windows NT.	ISCA	1998	DBLP DOI BibTeX RDF
36	Kenneth M. Wilson, Kunle Olukotun	High Bandwidth On-Chip Cache Design.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Dynamic superscalar, banked cache, dual-ported cache, SPEC95, memory bandwidth
28	Yonggang Che, Zhenghua Wang	A Lightweight Iterative Compilation Approach for Optimization Parameter Selection.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF
28	Mauro Olivieri	Design of synchronous and asynchronous variable-latency pipelined multipliers.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
28	Nigel P. Topham, Antonio González 0001	Randomized Cache Placement for Eliminating Conflicts.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Conflict avoidance, performance evaluation, cache architectures
28	Akhilesh Tyagi, Hon-Chi Ng, Prasant Mohapatra	Dynamic Branch Decoupled Architecture.	ICCD	1999	DBLP DOI BibTeX RDF	dynamic, decoupling, branches
28	Olivier Temam	Investigating Optimal Local Memory Performance.	ASPLOS	1998	DBLP DOI BibTeX RDF
28	David W. Goodwin	Interprocedural Dataflow Analysis in an Executable Optimizer.	PLDI	1997	DBLP DOI BibTeX RDF
28	Thomas Ball, James R. Larus	Efficient Path Profiling.	MICRO	1996	DBLP DOI BibTeX RDF
14	Lili Pan 0002, Beiji Zou, Hao Chen 0051, Haoyu Zhou	Research on Translucent Mechanism-Based Infeasible Path.	ICYCS	2008	DBLP DOI BibTeX RDF
14	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Reducing Data TLB Power via Compiler-Directed Address Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
14	Jaeheon Jeong, Per Stenström, Michel Dubois 0001	Simple penalty-sensitive replacement policies for caches.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	cache, memory system, replacement policy, penalty
14	Emil Talpes, Diana Marculescu	Execution cache-based microarchitecture for power-efficient superscalar processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
14	Thi Viet Nga Nguyen, François Irigoin	Efficient and effective array bound checking.	ACM Trans. Program. Lang. Syst.	2005	DBLP DOI BibTeX RDF	interprocedural analysis, Array bound checking
14	Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David M. Brooks	A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance.	MICRO	2005	DBLP DOI BibTeX RDF
14	Kiruthika Selvamani, Tarek M. Taha	Estimating critical region parallelism to guide platform retargeting.	ACM Southeast Regional Conference (1)	2005	DBLP DOI BibTeX RDF	analytical model, performance prediction
14	Seung Woo Son 0001, Guangyu Chen, Mahmut T. Kandemir	Disk layout optimization for reducing energy consumption.	ICS	2005	DBLP DOI BibTeX RDF	low power, optimizing compiler, disk layout
14	Karthik Pattabiraman, Zbigniew Kalbarczyk, Ravishankar K. Iyer	Application-Based Metrics for Strategic Placement of Detectors.	PRDC	2005	DBLP DOI BibTeX RDF
14	Qing Zhao, David J. Lilja	Static Classification of Value Predictability Using Compiler Hints.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
14	Allan Hartstein, Thomas R. Puzak	The optimum pipeline depth considering both power and performance.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Pipeline Depth, Power and Performance, Workload Specificity, Simulation
14	Jun Yang 0002, Rajiv Gupta 0001, Chuanjun Zhang	Frequent value encoding for low power data buses.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	I/O pin capacitance, Low power data buses, internal capacitance, encoding, switching
14	Rahul Joshi, Michael D. Bond, Craig B. Zilles	Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems.	CGO	2004	DBLP DOI BibTeX RDF
14	Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam	Compiler-directed physical address generation for reducing dTLB power.	ISPASS	2004	DBLP DOI BibTeX RDF
14	Georgios Dimitriou, Constantine D. Polychronopoulos	Loop Scheduling for Multithreaded Processors.	PARELEC	2004	DBLP DOI BibTeX RDF
14	Martin Kämpe, Per Stenström, Michel Dubois 0001	Self-correcting LRU replacement policies.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	LRU algorithms, mistake prediction, shadow directories
14	Michel Dubois 0001	Fighting the memory wall with assisted execution.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	prefetching, cache memories, superscalar processors, simultaneous multithreading, latency tolerance
14	Lu Peng 0001, Jih-Kwon Peir, Qianrong Ma, Konrad Lai	Address-free memory access based on program syntax correlation of loads and stores.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
14	Ramaswamy Govindarajan, Hongbo Yang, José Nelson Amaral, Chihong Zhang, Guang R. Gao	Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	code sequence optimization, code generation, Compiler optimization, instruction level parallelism, register allocation, instruction scheduling, superscalar architectures
14	Anthony-Trung Nguyen, Josep Torrellas	Design Trade-Offs in High-Throughput Coherence Controllers.	IEEE PACT	2003	DBLP DOI BibTeX RDF
14	Allan Hartstein, Thomas R. Puzak	Optimum Power/Performance Pipeline Depth.	MICRO	2003	DBLP DOI BibTeX RDF
14	Lei Chen 0021, Steve Dropsho, David H. Albonesi	Dynamic Data Dependence Tracking and its Application to Branch Prediction.	HPCA	2003	DBLP DOI BibTeX RDF
14	Thi Viet Nga Nguyen, François Irigoin, Corinne Ancourt, Fabien Coelho	Automatic Detection of Uninitialized Variables.	CC	2003	DBLP DOI BibTeX RDF
14	Jianwei Chen, Michel Dubois 0001, Per Stenström	Integrating complete-system and user-level performance/power simulators: the SimWattch approach.	ISPASS	2003	DBLP DOI BibTeX RDF
14	Mondira Deb Pant, Pankaj Pant, D. Scott Wills	On-chip decoupling capacitor optimization using architectural level prediction.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
14	Jun Yang 0002, Rajiv Gupta 0001	Energy efficient frequent value data cache design.	MICRO	2002	DBLP DOI BibTeX RDF
14	Martin Kämpe, Per Stenström, Michel Dubois 0001	The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.	HPCA	2002	DBLP DOI BibTeX RDF	Discrete Fourier Transform, Branch Prediction, Dynamically Scheduled Processors
14	Linda M. Wills, Tarek M. Taha, Lewis Benton Baumstark Jr., D. Scott Wills	Estimating Potential Parallelism for Platform Retargeting.	WCRE	2002	DBLP DOI BibTeX RDF
14	Chi-Hung Chi, Jun-Li Yuan	Runtime Association of Software Prefetch Control to Memory Access Instructions (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
14	Nikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka	Efficient Power Reduction Techniques for Time Multiplexed Address Buses.	ISSS	2002	DBLP DOI BibTeX RDF	address encoding techniques, time-multiplexed addressing, low power
14	Weiyu Tang, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta 0001	Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption.	ISHPC	2002	DBLP DOI BibTeX RDF
14	Amirali Baniasadi, Andreas Moshovos	Asymmetric-frequency clustering: a power-aware back-end for high-performance processors.	ISLPED	2002	DBLP DOI BibTeX RDF	assymetric frequency clustering, high-performance processors, instruction criticality, processor back-end, power-aware architectures
14	T. N. Vijaykumar, Irith Pomeranz, Karl Cheng	Transient-Fault Recovery Using Simultaneous Multithreading.	ISCA	2002	DBLP DOI BibTeX RDF
14	Allan Hartstein, Thomas R. Puzak	The Optimum Pipeline Depth for a Microprocessor.	ISCA	2002	DBLP DOI BibTeX RDF
14	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	A High-Bandwidth Memory Pipeline for Wide Issue Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Data bandwidth, runtime stack, data stream partitioning, multiported data cache, instruction level parallelism, data locality
14	Markus Mock, Manuvir Das, Craig Chambers, Susan J. Eggers	Dynamic points-to sets: a comparison with static analyses and potential applications in program understanding and optimization.	PASTE	2001	DBLP DOI BibTeX RDF	calpa, dynamic analysis, program understanding, program optimization, points-to analysis, alias analysis, program instrumentation
14	Joydeep Ray, James C. Hoe, Babak Falsafi	Dual use of superscalar datapath for transient-fault detection and recovery.	MICRO	2001	DBLP DOI BibTeX RDF
14	Krishnan Kailas, Kemal Ebcioglu, Ashok K. Agrawala	CARS: A New Code Generation Framework for Clustered ILP Processors.	HPCA	2001	DBLP DOI BibTeX RDF
14	Peter van Beek, Kent D. Wilken	Fast Optimal Instruction Scheduling for Single-Issue Processors with Arbitrary Latencies.	CP	2001	DBLP DOI BibTeX RDF
14	Zhenyu Tang, Lei He 0001, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa	Instruction Prediction for Step Power Reduction.	ISQED	2001	DBLP DOI BibTeX RDF
14	Renato J. O. Figueiredo, José A. B. Fortes	Hardware Support for Extracting Coarse-Grain Speculative Parallelism in Distributed Shared-Memory Multiprocessors.	ICPP	2001	DBLP DOI BibTeX RDF
14	Humayun Khalid	Validating Trace-Driven Microarchitectural Simulations.	IEEE Micro	2000	DBLP DOI BibTeX RDF
14	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos	Using dynamic cache management techniques to reduce energy in general purpose processors.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
14	Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He 0001	Ramp Up/Down Functional Unit to Reduce Step Power.	PACS	2000	DBLP DOI BibTeX RDF
14	Darko Stefanovic, Margaret Martonosi	On Availability of Bit-Narrow Operations in General-Purpose Applications.	FPL	2000	DBLP DOI BibTeX RDF
14	Thierry Lafage, André Seznec	Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
14	Kevin D. Rich, Matthew K. Farrens	The Decoupled-Style Prefetch Architecture (Research Note).	Euro-Par	2000	DBLP DOI BibTeX RDF
14	Manuvir Das	Unification-based pointer analysis with directional assignments.	PLDI	2000	DBLP DOI BibTeX RDF
14	Steven Lucco	Split-stream dictionary program compression.	PLDI	2000	DBLP DOI BibTeX RDF	virtual machine, compression, runtime system
14	Kent D. Wilken, Jack Liu, Mark Heffernan	Optimal instruction scheduling using integer programming.	PLDI	2000	DBLP DOI BibTeX RDF
14	Tao Li 0006, Lizy Kurian John, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Jyotsna Sabarinathan, Anupama Murthy	Using complete system simulation to characterize SPECjvm98 benchmarks.	ICS	2000	DBLP DOI BibTeX RDF	Java
14	Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari	Inductive Noise Reduction at the Architectural Level.	VLSI Design	2000	DBLP DOI BibTeX RDF	SIMD, superscalar, Clock-gating, Ground Bounce
14	Steven K. Reinhardt, Shubhendu S. Mukherjee	Transient fault detection via simultaneous multithreading.	ISCA	2000	DBLP DOI BibTeX RDF
14	Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg	Slipstream Processors: Improving both Performance and Fault Tolerance.	ASPLOS	2000	DBLP DOI BibTeX RDF
14	Eric Rotenberg, Steve Bennett, James E. Smith 0001	A Trace Cache Microarchitecture and Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching
14	Jih-Kwon Peir, Windsor W. Hsu, Alan Jay Smith	Functional Implementation Techniques for CPU Cache Memories.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	cache access mechanism, cache area and bandwidth, Cache memory, address translation
14	Olivier Temam	An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	Optimal memory management, Belady, cache, local memory
14	Soner Önder, Jun Xu, Rajiv Gupta 0001	Caching and Predicting Branch Sequences for Improved Fetch Effectiveness.	IEEE PACT	1999	DBLP DOI BibTeX RDF	branch sequence prediction, sequence table, fetch bandwidth, speculative execution
14	Eric Rotenberg	AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors.	FTCS	1999	DBLP DOI BibTeX RDF	branch prediction and value prediction, trace processors, transient faults, simultaneous multithreading, time redundancy
14	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	Access Region Locality for High-Bandwidth Processor Memory System Design.	MICRO	1999	DBLP DOI BibTeX RDF
14	Timothy H. Heil, Zak Smith, James E. Smith 0001	Improving Branch Predictors by Correlating on Data Values.	MICRO	1999	DBLP DOI BibTeX RDF
14	Eric Rotenberg, James E. Smith 0001	Control Independence in Trace Processors.	MICRO	1999	DBLP DOI BibTeX RDF
14	B. Grayson, L. John, C. Chase	The effects of memory-access ordering on multiple-issue uniprocessor performance.	IPCCC	1999	DBLP DOI BibTeX RDF
14	Alan Pita, Nadeem Malik	Sectored renaming for superscalar microprocessors.	IPCCC	1999	DBLP DOI BibTeX RDF
14	Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, Mithuna Thottethodi	Annotated Memory References: A Mechanism for Informed Cache Management.	Euro-Par	1999	DBLP DOI BibTeX RDF
14	Thierry Lafage, André Seznec, Erven Rohou, François Bodin	Code Cloning Tracing: A "Pay per Trace" Approach.	Euro-Par	1999	DBLP DOI BibTeX RDF
14	Chi-Hung Chi, Jun-Li Yuan	Design Considerations of High Performance Data Cache with Prefetching.	Euro-Par	1999	DBLP DOI BibTeX RDF
14	David L. Rhodes, Wayne H. Wolf	Unbalanced Cache Systems.	MTDT	1999	DBLP DOI BibTeX RDF
14	Chi-Hung Chi, Jun-Li Yuan	Sequential Unification and Aggressive Lookahead Mechanisms for Data Memory Accesses.	PaCT	1999	DBLP DOI BibTeX RDF
14	Rastislav Bodík, Rajiv Gupta 0001, Mary Lou Soffa	Load-Reuse Analysis: Design and Evaluation.	PLDI	1999	DBLP DOI BibTeX RDF	data-flow analysis, program representations, profile-guided optimizations, register promotion
14	Le-Chun Wu, Rajiv Mirani, Harish Patil, Bruce Olsen, Wen-mei W. Hwu	A New Framework for Debugging Globally Optimized Code.	PLDI	1999	DBLP DOI BibTeX RDF
14	Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis	Energy and Performance Improvements in Microprocessor Design Using a Loop Cache.	ICCD	1999	DBLP DOI BibTeX RDF
14	Chi-Hung Chi, Jun-Li Yuan	Load-Balancing Branch Target Cache and Prefetch Buffer.	ICCD	1999	DBLP DOI BibTeX RDF	branch target cache, load-balancing, Memory, prefetching, instruction cache
14	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor.	ISCA	1999	DBLP DOI BibTeX RDF
14	Matthew C. Merten, Andrew R. Trick, Christopher N. George, John C. Gyllenhaal, Wen-mei W. Hwu	A Hardware-Driven Profiling Scheme for Identifying Program Hot Spots to Support Runtime Optimization.	ISCA	1999	DBLP DOI BibTeX RDF
14	Jozo J. Dujmovic, Ivo Dujmovic	Evolution and evaluation of SPEC benchmarks.	SIGMETRICS Perform. Evaluation Rev.	1998	DBLP DOI BibTeX RDF
14	Steven Wallace, Nader Bagherzadeh	Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
14	Glenn Ammons, James R. Larus	Improving Data-flow Analysis with Path Profiles.	PLDI	1998	DBLP DOI BibTeX RDF
14	Gabriel Rivera, Chau-Wen Tseng	Data Transformations for Eliminating Conflict Misses.	PLDI	1998	DBLP DOI BibTeX RDF
14	Glenn Ammons, James R. Larus	Improving data-flow analysis with path profiles (with retrospective)	Best of PLDI	1998	DBLP DOI BibTeX RDF
14	Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos	Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors.	ISLPED	1998	DBLP DOI BibTeX RDF
14	Cristina Cifuentes, Doug Simon, Antoine Fraboulet	Assembly to High-Level Language Translation.	ICSM	1998	DBLP DOI BibTeX RDF
14	Yiannakis Sazeides, James E. Smith 0001	Modeling Program Predictability.	ISCA	1998	DBLP DOI BibTeX RDF
14	Jih-Kwon Peir, Yongjoon Lee, Windsor W. Hsu	Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology.	ASPLOS	1998	DBLP DOI BibTeX RDF
14	Yiannakis Sazeides, James E. Smith 0001	The Predictability of Data Values.	MICRO	1997	DBLP DOI BibTeX RDF	Context Based Prediction, Stride Prediction, Last Value Prediction, Prediction, Value Prediction
14	Steven Wallace, Nader Bagherzadeh	Multiple Branch and Block Prediction.	HPCA	1997	DBLP DOI BibTeX RDF
14	Jens Simon, Marco Vieth, Reinhold Weicker	Workload Analysis of Computation Intensive Tasks: Case Study on SPEC CPU95 Benchmarks.	Euro-Par	1997	DBLP DOI BibTeX RDF
14	José González 0002, Antonio González 0001	Memory Address Prediction for Data Speculation.	Euro-Par	1997	DBLP DOI BibTeX RDF
14	Tim A. Wagner, Susan L. Graham	Incremental Analysis of real Programming Languages.	PLDI	1997	DBLP DOI BibTeX RDF