Search results for "SPUR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	Yoshinori Akao, Atsushi Yamamoto, Yoshiyasu Higashikawa	Estimation of Inkjet Printer Spur Gear Teeth Number from Pitch Data String of Limited Length.	IWCF	2009	DBLP DOI BibTeX RDF	forensic document analysis, inkjet printer identification, spur mark comparison method, spectral analysis, pitch, maximum entropy method
93	Anne Marchant, Bill Tulloh	Using pre-release software to SPUR student learning.	SIGITE Conference	2005	DBLP DOI BibTeX RDF	SPUR, security, IT education, software evaluation
91	Takeshi Furukawa	Detecting the Spur Marks of Ink-Jet Printed Documents Using a Multiband Scanner in NIR Mode and Image Restoration.	IWCF	2009	DBLP DOI BibTeX RDF
88	Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson	RISCs versus CISCs for Prolog: A Case Study.	ASPLOS	1987	DBLP DOI BibTeX RDF	Prolog, RISC, CISC
62	K. Venkatesh Prasad, Thomas J. Giuli, David Watson	The Case for Modeling Security, Privacy, Usability and Reliability (SPUR) in Automotive Software.	ASWSD	2006	DBLP DOI BibTeX RDF
54	Cheng-Ru Ho, Mike Shuo-Wei Chen	A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
54	Cheng-Ru Ho, Mike Shuo-Wei Chen	10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS.	ISSCC	2016	DBLP DOI BibTeX RDF
45	Douglas Johnson	Trap Architectures for Lisp Systems.	LISP and Functional Programming	1990	DBLP DOI BibTeX RDF	SPUR, LISP, RISC
44	David A. Patterson 0001	Viewpoint - Your students are your legacy.	Commun. ACM	2009	DBLP DOI BibTeX RDF
44	Dan Zhang, Zeng-zhi Li, Hong Song, Long Liu	A Programming Model for an Embedded Media Processing Architecture.	SAMOS	2005	DBLP DOI BibTeX RDF
36	Maxim Spur, Vincent Tourre, Erwan J. David, Guillaume Moreau, Patrick Le Callet	Exploring Multiple and Coordinated Views for Multilayered Geospatial Data in Virtual Reality.	Inf.	2020	DBLP DOI BibTeX RDF
36	N. Spur, E. Kranjec, M. Puhek, K. Breznik, L. Klasinc, S. Frumen	University teachers' needs for the efficient use of ICT in the pedagogical process.	MIPRO	2020	DBLP DOI BibTeX RDF
36	Maxim Spur, Vincent Tourre, Erwan J. David, Guillaume Moreau, Patrick Le Callet	MapStack: Exploring Multilayered Geospatial Data in Virtual Reality.	VISIGRAPP (3: IVAPP)	2020	DBLP DOI BibTeX RDF
36	Maxim Spur, Vincent Tourre, Jimmy Coppin	Virtually physical presentation of data layers for spatiotemporal urban data visualization.	VSMM	2017	DBLP DOI BibTeX RDF
36	Günter Spur, Kai Mertins, R. Albrecht, F. Duttenhofer, H. Edeler, Roland Jochem, H. Kopp-Jung, Markus Rabe 0001, Burkhard Schallock, U. Wegener	Introductory Overview.	Information Management in Computer Integrated Manufacturing	1995	DBLP DOI BibTeX RDF
36	Günter Spur, Sabine Weiß	Application of Model-based Diagnosis to Machine Tools.	Expert Systems in Engineering	1990	DBLP DOI BibTeX RDF
36	Günter Spur	Advanced Design for Automated Manufacture.	IFIP Congress	1989	DBLP BibTeX RDF
36	G. Spur, G. Seliger, I. Furgac, T. V. Diep	Sensorunterstütztes Montagesystem.	Robotersysteme	1986	DBLP BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, H. Hoffmann	Baustein GEOMETRIE.	Comput. Graph.	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, H.-M. Anger	Working Techniques of Computer-Aided Process Planning.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, W. Grottke	Planning of Assembly Sequences.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, L. Sidarous	Programming of Robots Using Graphical Techniques.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, W. Grottke	Graphical Simulation of Manufacturing Processes in Process Planning.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, Winfried Turowski	Methodology of Process Planning.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, Winfried Turowski	The Capsy Process Planning System.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, W. Grottke	Integrated Aspects of Technological Planning.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, Winfried Turowski	N/C-Technology.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, L. Sidarous	Development of APT and EXAPT.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, H.-M. Anger	Systems for Computer Aided Process Planning Including Quality Control.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, Winfried Turowski	N/C-Programming on the Shop Floor Using Graphical Simulation Techniques.	Methods and Tools for Computer Integrated Manufacturing	1983	DBLP DOI BibTeX RDF
36	Günter Spur, Frank-Lothar Krause, H. Hoffmann	Systemarchitektur und Leistungsspektrum des Bausteins GEOMETRIE.	Geometrisches Modellieren	1982	DBLP DOI BibTeX RDF
36	Yixi Li, Zhao Zhang 0004, Yong Chen 0005, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM.	A-SSCC	2023	DBLP DOI BibTeX RDF
36	Zexin Yuan, Lei Zhang 0033, Yan Wang 0023	A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper.	ISCAS	2021	DBLP DOI BibTeX RDF
36	Yi-An Li, Ali M. Niknejad	A 138Fsrms-Integrated-Jitter and -249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
36	Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho	14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.	ISSCC	2015	DBLP DOI BibTeX RDF
36	Mohamed M. Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio	A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
36	Al-Said Samer Abedallah Masoud, Mohammad Qasim	Increasing spur gear durability: two-material spur gear.	Int. J. Comput. Appl. Technol.	2005	DBLP DOI BibTeX RDF
33	Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram	A low spur fractional-N frequency synthesizer architecture.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
33	David A. Wood 0001, Randy H. Katz	Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache.	ISCA	1989	DBLP DOI BibTeX RDF
33	James R. Larus, Paul N. Hilfinger	Register allocation in the SPUR Lisp compiler.	SIGPLAN Symposium on Compiler Construction	1986	DBLP DOI BibTeX RDF	LISP, LISP
29	David A. Wood 0001, Garth A. Gibson, Randy H. Katz	Verifying a Multiprocessor Cache Controller Using Random Test Generation.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
29	Wen-mei W. Hwu, Yale N. Patt	Exploiting horizontal and vertical concurrency via the HPSm microprocessor.	MICRO	1987	DBLP DOI BibTeX RDF
18	Rafael E. Tuirán Villalba, Heriberto Maury Ramírez, Héctor Águila Estrada, José A. Oñate López, AndréS F. Ruge González, Katerin Osorio Barrera, Luis G. Riveros Almanza, Daniel E. Espinosa Corrales	Effect of Combined Misalignments on Vibrations of a Single-Stage Spur Gear Transmission System: An Experimental Approach.	IEEE Access	2024	DBLP DOI BibTeX RDF
18	Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang	A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
18	Farnaz Rezay Morsagh, Mehdi Siahi, Soudabeh Soleymani	Synchronization and Control of Chaotic Spur Gear System Using Type-II Fuzzy Controller Optimized via Whale Optimization Algorithm.	CoRR	2024	DBLP DOI BibTeX RDF
18	Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi	10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Hangil Choi, SeongHwan Cho	19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada	10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin	10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Yunbo Huang, Yong Chen 0005, Zunsong Yang, Rui Paulo Martins, Pui-In Mak	7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Marichamy Divya, Siva Kumar Rapina, S. Kumaravel 0001	Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications.	VLSID	2024	DBLP DOI BibTeX RDF
18	Kyumin Kwon, Omar A. B. Abdelatty, David D. Wentzloff	PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie	A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
18	Ketaki Joshi, Bhushan Patil	Automated inspection of spur gears using machine vision approach.	Int. J. Comput. Vis. Robotics	2023	DBLP DOI BibTeX RDF
18	Stelian Cazan, Shubrajit Bhaumik, Viorel Paleu, Spiridon Cretu	Developing a Fast-Processing Novel Algorithm for Contact Analysis of Standard Spur Gears.	Symmetry	2023	DBLP DOI BibTeX RDF
18	Hao Liu, Dayi Zhang, Kaicheng Liu, Jianjun Wang, Yu Liu, Yifu Long	Nonlinear Dynamic Modeling and Analysis for a Spur Gear System with Dynamic Meshing Parameters and Sliding Friction.	Symmetry	2023	DBLP DOI BibTeX RDF
18	Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu	A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
18	Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins	A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
18	Emre Ulusoy, Ertan Zencir	A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
18	Jinwei Li, Bing Sun, Jiawei Huang, Hudong Chang, Rui Jia, Honggang Liu	A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur -81.1 dBc in 0.13 μm CMOS technology.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
18	Zirui Jin, Xiaoyu Shan, Ang Hu, Dongsheng Liu, Xuan Cheng, Jinsong Cui, Chengcheng Zhang, Jianming Lei	A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications.	Microelectron. J.	2023	DBLP DOI BibTeX RDF
18	Daxin Sun, Saixing Zeng, Hanyang Ma, Jonathan Jingsheng Shi	How Do High-Speed Railways Spur Innovation?	IEEE Trans. Engineering Management	2023	DBLP DOI BibTeX RDF
18	Christos Kalligeros, Christos Papalexis, Georgios Vasileiou, Panteleimon Tzouganakis, Christos Spitas, Vasilios Spitas	Exploiting double-flank roll testing spur gear measurements to determine gear parameter deviations through numerical simulation of free-form meshing gears.	Simul. Model. Pract. Theory	2023	DBLP DOI BibTeX RDF
18	Zhichao Zhang, Wenjie Zheng, Xinlin Xia, Yanjie Wang	A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
18	Long Chen, Wenhua Chen, Xiaofan Chen, Youjiang Liu, Fadhel M. Ghannouchi, Zhenghe Feng	Spur-Free Harmonic Cancelation Digital Predistortion for HF Transmitters.	IEEE Commun. Lett.	2023	DBLP DOI BibTeX RDF
18	Tanner Tengberg, Hua Zhang, Ayman A. Fayed	Spur-Free Switch-Mode Power Supplies.	MWSCAS	2023	DBLP DOI BibTeX RDF
18	Xu Lu, Michael Peter Kennedy	Further Insights into Spur Immunity in MASH-Based Fractional-N CP-PLLs with Polynomial Nonlinearities.	ICECS	2023	DBLP DOI BibTeX RDF
18	Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi	A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM.	ESSCIRC	2023	DBLP DOI BibTeX RDF
18	Xiaowen Shi, Xintian Liu	Wear Life Prediction of Spur Gear Transmission System Considering Roughness Influence.	ICSRS	2023	DBLP DOI BibTeX RDF
18	Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka	A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
18	Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi	A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
18	Jarrah Bergeron, Sudhakar Pamarti	A Spur-free Dynamic Element Matching Scheme for Bandpass DACs.	NEWCAS	2023	DBLP DOI BibTeX RDF
18	Chao Fan, Ya Zhao, Yanlong Zhang, Jun Yin, Pui-In Mak, Guohe Zhang, Li Geng	A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS.	CICC	2023	DBLP DOI BibTeX RDF
18	Shiwei Zhang, Wei Deng 0001, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi	A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS.	CICC	2023	DBLP DOI BibTeX RDF
18	Shengmao Zhou, Xin Yin, Hongshuai Hu, Guanglu Yang, Shuchao Bai, Dehai Zhang	Meshing Statics and Modification Analysis of Spur Gear Based On ABAQUS.	RICAI	2023	DBLP DOI BibTeX RDF
18	Zhao Zhang 0004, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu 0021, Yong Chen, Nanjian Wu, Liyuan Liu	A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen	A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino	A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Dawei Mai, Michael Peter Kennedy	Initial Condition-Dependent Spur Pattern Induced by Undithered MASH DDSM Divider Controller.	ISCAS	2023	DBLP DOI BibTeX RDF
18	Snigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena	A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications.	VLSID	2023	DBLP DOI BibTeX RDF
18	Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, Nagendra Krishnapura	A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur.	APCCAS	2023	DBLP DOI BibTeX RDF
18	Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Mike Keaveney	Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi	A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie	A Low-Jitter and Low-Spur Charge-Sampling PLL.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Rongjin Xu, Dawei Ye, Chuanjin Richard Shi	A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction.	Integr.	2022	DBLP DOI BibTeX RDF
18	K. Rameshkumar, R. Sriram, M. Saimurugan, P. Krishnakumar	Establishing Statistical Correlation Between Sensor Signature Features and Lubricant Solid Particle Contamination in a Spur Gearbox.	IEEE Access	2022	DBLP DOI BibTeX RDF
18	Zunsong Yang, Yong Chen 0005, Jia Yuan, Pui-In Mak, Rui Paulo Martins	A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
18	Lantao Yang, Qiuyuan Chen, Lei Yin, Liming Wang, Yimin Shao	Dynamic characteristic of spur gear system with spalling fault considering tooth pitch error.	Qual. Reliab. Eng. Int.	2022	DBLP DOI BibTeX RDF
18	Debdut Biswas	Spur Reduction Circuit for Fractional-N PLLs.	Circuits Syst. Signal Process.	2022	DBLP DOI BibTeX RDF
18	Valerio Mazzaro, Michael Peter Kennedy	A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Mohammad Ali Labbaf Khaniki, Mohammad Salehi Kho, Mahdi Aliyari Shoorehdeli	Control and synchronization of chaotic spur gear system using adaptive non-singular fast terminal sliding mode controller.	Trans. Inst. Meas. Control	2022	DBLP DOI BibTeX RDF
18	Wen-Cheng Lai	Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing.	Sensors	2022	DBLP DOI BibTeX RDF
18	Krishanu Gupta, Sushovan Chatterjee	Modal behaviour of spur gear pairs for a low speed transmission application - a comparative study between symmetric and asymmetric gears.	Int. J. Simul. Process. Model.	2022	DBLP DOI BibTeX RDF
18	Xiongjie Zhang, Yang Jiang 0002, Man-Kay Law, Pui-In Mak, Rui Paulo Martins	Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters.	PRIME	2022	DBLP DOI BibTeX RDF
18	Muhammad Sadeqi, Ali Sadollah, Seyed Morteza Razavi	Spur Gear Optimization Using Metaheuristics and Computer Aided Engineering Design.	ICHSA	2022	DBLP DOI BibTeX RDF
18	Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong	A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration.	ESSCIRC	2022	DBLP DOI BibTeX RDF
18	Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka	A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF