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Publication years (Num. hits)
1982-1986 (16) 1987-1992 (16) 1993-2000 (17) 2001-2004 (20) 2005-2006 (30) 2007-2008 (29) 2009 (20) 2010 (20) 2011 (21) 2012 (15) 2013 (19) 2014-2015 (31) 2016 (25) 2017 (23) 2018 (17) 2019 (32) 2020 (27) 2021 (24) 2022 (20) 2023 (34) 2024 (9)
Publication types (Num. hits)
article(192) incollection(1) inproceedings(270) phdthesis(2)
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The graphs summarize 91 occurrences of 84 keywords

Results
Found 469 publication records. Showing 465 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
122Yoshinori Akao, Atsushi Yamamoto, Yoshiyasu Higashikawa Estimation of Inkjet Printer Spur Gear Teeth Number from Pitch Data String of Limited Length. Search on Bibsonomy IWCF The full citation details ... 2009 DBLP  DOI  BibTeX  RDF forensic document analysis, inkjet printer identification, spur mark comparison method, spectral analysis, pitch, maximum entropy method
93Anne Marchant, Bill Tulloh Using pre-release software to SPUR student learning. Search on Bibsonomy SIGITE Conference The full citation details ... 2005 DBLP  DOI  BibTeX  RDF SPUR, security, IT education, software evaluation
91Takeshi Furukawa Detecting the Spur Marks of Ink-Jet Printed Documents Using a Multiband Scanner in NIR Mode and Image Restoration. Search on Bibsonomy IWCF The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
88Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson RISCs versus CISCs for Prolog: A Case Study. Search on Bibsonomy ASPLOS The full citation details ... 1987 DBLP  DOI  BibTeX  RDF Prolog, RISC, CISC
62K. Venkatesh Prasad, Thomas J. Giuli, David Watson The Case for Modeling Security, Privacy, Usability and Reliability (SPUR) in Automotive Software. Search on Bibsonomy ASWSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Cheng-Ru Ho, Mike Shuo-Wei Chen A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
54Cheng-Ru Ho, Mike Shuo-Wei Chen 10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
45Douglas Johnson Trap Architectures for Lisp Systems. Search on Bibsonomy LISP and Functional Programming The full citation details ... 1990 DBLP  DOI  BibTeX  RDF SPUR, LISP, RISC
44David A. Patterson 0001 Viewpoint - Your students are your legacy. Search on Bibsonomy Commun. ACM The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
44Dan Zhang, Zeng-zhi Li, Hong Song, Long Liu A Programming Model for an Embedded Media Processing Architecture. Search on Bibsonomy SAMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Maxim Spur, Vincent Tourre, Erwan J. David, Guillaume Moreau, Patrick Le Callet Exploring Multiple and Coordinated Views for Multilayered Geospatial Data in Virtual Reality. Search on Bibsonomy Inf. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
36N. Spur, E. Kranjec, M. Puhek, K. Breznik, L. Klasinc, S. Frumen University teachers' needs for the efficient use of ICT in the pedagogical process. Search on Bibsonomy MIPRO The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
36Maxim Spur, Vincent Tourre, Erwan J. David, Guillaume Moreau, Patrick Le Callet MapStack: Exploring Multilayered Geospatial Data in Virtual Reality. Search on Bibsonomy VISIGRAPP (3: IVAPP) The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
36Maxim Spur, Vincent Tourre, Jimmy Coppin Virtually physical presentation of data layers for spatiotemporal urban data visualization. Search on Bibsonomy VSMM The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
36Günter Spur, Kai Mertins, R. Albrecht, F. Duttenhofer, H. Edeler, Roland Jochem, H. Kopp-Jung, Markus Rabe 0001, Burkhard Schallock, U. Wegener Introductory Overview. Search on Bibsonomy Information Management in Computer Integrated Manufacturing The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
36Günter Spur, Sabine Weiß Application of Model-based Diagnosis to Machine Tools. Search on Bibsonomy Expert Systems in Engineering The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
36Günter Spur Advanced Design for Automated Manufacture. Search on Bibsonomy IFIP Congress The full citation details ... 1989 DBLP  BibTeX  RDF
36G. Spur, G. Seliger, I. Furgac, T. V. Diep Sensorunterstütztes Montagesystem. Search on Bibsonomy Robotersysteme The full citation details ... 1986 DBLP  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, H. Hoffmann Baustein GEOMETRIE. Search on Bibsonomy Comput. Graph. The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, H.-M. Anger Working Techniques of Computer-Aided Process Planning. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, W. Grottke Planning of Assembly Sequences. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, L. Sidarous Programming of Robots Using Graphical Techniques. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, W. Grottke Graphical Simulation of Manufacturing Processes in Process Planning. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, Winfried Turowski Methodology of Process Planning. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, Winfried Turowski The Capsy Process Planning System. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, W. Grottke Integrated Aspects of Technological Planning. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, Winfried Turowski N/C-Technology. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, L. Sidarous Development of APT and EXAPT. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, H.-M. Anger Systems for Computer Aided Process Planning Including Quality Control. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, Winfried Turowski N/C-Programming on the Shop Floor Using Graphical Simulation Techniques. Search on Bibsonomy Methods and Tools for Computer Integrated Manufacturing The full citation details ... 1983 DBLP  DOI  BibTeX  RDF
36Günter Spur, Frank-Lothar Krause, H. Hoffmann Systemarchitektur und Leistungsspektrum des Bausteins GEOMETRIE. Search on Bibsonomy Geometrisches Modellieren The full citation details ... 1982 DBLP  DOI  BibTeX  RDF
36Yixi Li, Zhao Zhang 0004, Yong Chen 0005, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. Search on Bibsonomy A-SSCC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
36Zexin Yuan, Lei Zhang 0033, Yan Wang 0023 A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper. Search on Bibsonomy ISCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
36Yi-An Li, Ali M. Niknejad A 138Fsrms-Integrated-Jitter and -249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS. Search on Bibsonomy VLSI Circuits The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
36Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho 14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. Search on Bibsonomy ISSCC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
36Mohamed M. Elsayed, Mohammed M. Abdul-Latif, Edgar Sánchez-Sinencio A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
36Al-Said Samer Abedallah Masoud, Mohammad Qasim Increasing spur gear durability: two-material spur gear. Search on Bibsonomy Int. J. Comput. Appl. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram A low spur fractional-N frequency synthesizer architecture. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33David A. Wood 0001, Randy H. Katz Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache. Search on Bibsonomy ISCA The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
33James R. Larus, Paul N. Hilfinger Register allocation in the SPUR Lisp compiler. Search on Bibsonomy SIGPLAN Symposium on Compiler Construction The full citation details ... 1986 DBLP  DOI  BibTeX  RDF LISP, LISP
29David A. Wood 0001, Garth A. Gibson, Randy H. Katz Verifying a Multiprocessor Cache Controller Using Random Test Generation. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
29Wen-mei W. Hwu, Yale N. Patt Exploiting horizontal and vertical concurrency via the HPSm microprocessor. Search on Bibsonomy MICRO The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
18Rafael E. Tuirán Villalba, Heriberto Maury Ramírez, Héctor Águila Estrada, José A. Oñate López, AndréS F. Ruge González, Katerin Osorio Barrera, Luis G. Riveros Almanza, Daniel E. Espinosa Corrales Effect of Combined Misalignments on Vibrations of a Single-Stage Spur Gear Transmission System: An Experimental Approach. Search on Bibsonomy IEEE Access The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Jianguo Hu, Renfei Zou, Yao Yao, Jiajun He, Deming Wang A 2.4-GHz ring-VCO-based time-to-voltage conversion PLL achieving low-jitter and low-spur performance. Search on Bibsonomy Microelectron. J. The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Farnaz Rezay Morsagh, Mehdi Siahi, Soudabeh Soleymani Synchronization and Control of Chaotic Spur Gear System Using Type-II Fuzzy Controller Optimized via Whale Optimization Algorithm. Search on Bibsonomy CoRR The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Yuhwan Shin, Junseok Lee, Juyeop Kim, Yongwoo Jo, Jaehyouk Choi 10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Hangil Choi, SeongHwan Cho 19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, Micheál Scully, Niall McDermott, James Breslin 10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Yunbo Huang, Yong Chen 0005, Zunsong Yang, Rui Paulo Martins, Pui-In Mak 7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur. Search on Bibsonomy ISSCC The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Marichamy Divya, Siva Kumar Rapina, S. Kumaravel 0001 Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications. Search on Bibsonomy VLSID The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
18Kyumin Kwon, Omar A. B. Abdelatty, David D. Wentzloff PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen 0022, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, -258.7-dB FOM, and -75.17-dBc Reference Spur. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Ketaki Joshi, Bhushan Patil Automated inspection of spur gears using machine vision approach. Search on Bibsonomy Int. J. Comput. Vis. Robotics The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Stelian Cazan, Shubrajit Bhaumik, Viorel Paleu, Spiridon Cretu Developing a Fast-Processing Novel Algorithm for Contact Analysis of Standard Spur Gears. Search on Bibsonomy Symmetry The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Hao Liu, Dayi Zhang, Kaicheng Liu, Jianjun Wang, Yu Liu, Yifu Long Nonlinear Dynamic Modeling and Analysis for a Spur Gear System with Dynamic Meshing Parameters and Sliding Friction. Search on Bibsonomy Symmetry The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Teng-Shen Yang, Huai-Yuan Hsieh, Liang-Hung Lu A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Yunbo Huang, Yong Chen 0005, Bo Zhao 0003, Pui-In Mak, Rui Paulo Martins A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Emre Ulusoy, Ertan Zencir A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Jinwei Li, Bing Sun, Jiawei Huang, Hudong Chang, Rui Jia, Honggang Liu A 7.6-12.3 GHz wide-band PLL with an ultra low reference spur -81.1 dBc in 0.13 μm CMOS technology. Search on Bibsonomy Int. J. Circuit Theory Appl. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Zirui Jin, Xiaoyu Shan, Ang Hu, Dongsheng Liu, Xuan Cheng, Jinsong Cui, Chengcheng Zhang, Jianming Lei A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications. Search on Bibsonomy Microelectron. J. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Daxin Sun, Saixing Zeng, Hanyang Ma, Jonathan Jingsheng Shi How Do High-Speed Railways Spur Innovation? Search on Bibsonomy IEEE Trans. Engineering Management The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Christos Kalligeros, Christos Papalexis, Georgios Vasileiou, Panteleimon Tzouganakis, Christos Spitas, Vasilios Spitas Exploiting double-flank roll testing spur gear measurements to determine gear parameter deviations through numerical simulation of free-form meshing gears. Search on Bibsonomy Simul. Model. Pract. Theory The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Zhichao Zhang, Wenjie Zheng, Xinlin Xia, Yanjie Wang A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Long Chen, Wenhua Chen, Xiaofan Chen, Youjiang Liu, Fadhel M. Ghannouchi, Zhenghe Feng Spur-Free Harmonic Cancelation Digital Predistortion for HF Transmitters. Search on Bibsonomy IEEE Commun. Lett. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Tanner Tengberg, Hua Zhang, Ayman A. Fayed Spur-Free Switch-Mode Power Supplies. Search on Bibsonomy MWSCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Xu Lu, Michael Peter Kennedy Further Insights into Spur Immunity in MASH-Based Fractional-N CP-PLLs with Polynomial Nonlinearities. Search on Bibsonomy ICECS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Jiwon Shin, Joonghyun Song, Jihee Kim, Woo-Seok Choi A Near-Threshold Ring-Oscillator-Based ILCM with Edge-Selective Error Detector Achieving -64 dBc Reference-Spur and -239 dB FoM. Search on Bibsonomy ESSCIRC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Xiaowen Shi, Xintian Liu Wear Life Prediction of Spur Gear Transmission System Considering Roughness Influence. Search on Bibsonomy ICSRS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Yoonseo Cho, Jeonghyun Lee, Suneui Park, Seyeon Yoo, Jaehyouk Choi A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102 - Multiplication Factor Using a Power-Gating Technique. Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Jarrah Bergeron, Sudhakar Pamarti A Spur-free Dynamic Element Matching Scheme for Bandpass DACs. Search on Bibsonomy NEWCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Chao Fan, Ya Zhao, Yanlong Zhang, Jun Yin, Pui-In Mak, Guohe Zhang, Li Geng A 13.5-to-28.8GHz 72.3%-Locking Range Multi-Phase Injection-Locked Frequency Tripler with Improved Output Power and Wideband Subharmonic-Spur Rejection in 28nm CMOS. Search on Bibsonomy CICC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Shiwei Zhang, Wei Deng 0001, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. Search on Bibsonomy CICC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Shengmao Zhou, Xin Yin, Hongshuai Hu, Guanglu Yang, Shuchao Bai, Dehai Zhang Meshing Statics and Modification Analysis of Spur Gear Based On ABAQUS. Search on Bibsonomy RICAI The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Zhao Zhang 0004, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu 0021, Yong Chen, Nanjian Wu, Liyuan Liu A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. Search on Bibsonomy ISSCC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. Search on Bibsonomy ISSCC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Giacomo Castoro, Simone Mattia Dartizio, Francesco Tesolin, Francesco Buccoleri, Michele Rossoni, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. Search on Bibsonomy ISSCC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Simone Mattia Dartizio, Francesco Tesolin, Giacomo Castoro, Francesco Buccoleri, Luca Lanzoni, Michele Resson, Dmytro Cherniak, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. Search on Bibsonomy ISSCC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Dawei Mai, Michael Peter Kennedy Initial Condition-Dependent Spur Pattern Induced by Undithered MASH DDSM Divider Controller. Search on Bibsonomy ISCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Snigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications. Search on Bibsonomy VLSID The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Soumith Kusumanchi, Srinivas Theertham, Arpan Thakkar, Nagendra Krishnapura A 17 GHz Output PLL-Based Frequency Doubler with -60dBc Fundamental Spur. Search on Bibsonomy APCCAS The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
18Dawei Mai, Yann Donnelly, Michael Peter Kennedy, Stefano Tulisi, James Breslin, Patrick Griffin, Michael Connor, Stephen Brookes, Brian Shelly, Mike Keaveney Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Chanwoong Hwang, Hangi Park, Yongsun Lee, Taeho Seong, Jaehyouk Choi A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Jiang Gong, Edoardo Charbon, Fabio Sebastiano, Masoud Babaie A Low-Jitter and Low-Spur Charge-Sampling PLL. Search on Bibsonomy IEEE J. Solid State Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Rongjin Xu, Dawei Ye, Chuanjin Richard Shi A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Search on Bibsonomy Integr. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18K. Rameshkumar, R. Sriram, M. Saimurugan, P. Krishnakumar Establishing Statistical Correlation Between Sensor Signature Features and Lubricant Solid Particle Contamination in a Spur Gearbox. Search on Bibsonomy IEEE Access The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Zunsong Yang, Yong Chen 0005, Jia Yuan, Pui-In Mak, Rui Paulo Martins A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Lantao Yang, Qiuyuan Chen, Lei Yin, Liming Wang, Yimin Shao Dynamic characteristic of spur gear system with spalling fault considering tooth pitch error. Search on Bibsonomy Qual. Reliab. Eng. Int. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Debdut Biswas Spur Reduction Circuit for Fractional-N PLLs. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Valerio Mazzaro, Michael Peter Kennedy A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Mohammad Ali Labbaf Khaniki, Mohammad Salehi Kho, Mahdi Aliyari Shoorehdeli Control and synchronization of chaotic spur gear system using adaptive non-singular fast terminal sliding mode controller. Search on Bibsonomy Trans. Inst. Meas. Control The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Wen-Cheng Lai Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing. Search on Bibsonomy Sensors The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Krishanu Gupta, Sushovan Chatterjee Modal behaviour of spur gear pairs for a low speed transmission application - a comparative study between symmetric and asymmetric gears. Search on Bibsonomy Int. J. Simul. Process. Model. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Xiongjie Zhang, Yang Jiang 0002, Man-Kay Law, Pui-In Mak, Rui Paulo Martins Modelling and Analysis of ΔΣ-Modulation-Based Output Spectrum Spur Reduction in Dual-Path Hybrid DC-DC Converters. Search on Bibsonomy PRIME The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Muhammad Sadeqi, Ali Sadollah, Seyed Morteza Razavi Spur Gear Optimization Using Metaheuristics and Computer Aided Engineering Design. Search on Bibsonomy ICHSA The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. Search on Bibsonomy ESSCIRC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
18Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. Search on Bibsonomy VLSI Technology and Circuits The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
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