Search results for "Scheduling/Allocation"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha	Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling.	ASIAN	2004	DBLP DOI BibTeX RDF	Imprecise Design Exploration, Scheduling/Allocation, Multiple design attributes, Register constraint, Inclusion Scheduling, Imprecise information
25	Vyas Krishnan, Srinivas Katkoori	A genetic algorithm for the design space exploration of datapaths during high-level synthesis.	IEEE Trans. Evol. Comput.	2006	DBLP DOI BibTeX RDF
20	George A. Constantinides, Peter Y. K. Cheung, Wayne Luk	Optimum and heuristic synthesis of multiple word-length architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
20	Mehrdad Nourani, Christos A. Papachristou	Stability-based algorithms for high-level synthesis of digital ASICs.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
17	Raghava V. Cherabuddi, Jijun Chen, Magdy A. Bayoumi	A Graph-Based Approach to the Synthesis of Multi-Chip Module Architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF
15	Phan Cong Vinh, Jonathan P. Bowen	Formalization of Data Flow Computing and a Coinductive Approach to Verifying Flowware Synthesis.	Trans. Comput. Sci.	2008	DBLP DOI BibTeX RDF	Dynamically Programmable Field Array (DPGA), Flowware, Configware, Configware engineering, Embedded systems, Formal methods, Reconfigurable computing, Dynamic reconfiguration
14	Miodrag Potkonjak, Mani B. Srivastava	Behavioral optimization using the manipulation of timing constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
13	Mehrdad Nourani, Christos A. Papachristou	Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems.	DAC	1992	DBLP BibTeX RDF
12	Sujan Pandey, Rolf Drechsler	Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.	DATE	2008	DBLP DOI BibTeX RDF
12	Alexander D. Stoyen, Thomas J. Marlowe, Mohamed F. Younis, Plamen V. Petrov	A Development Environment for Complex Distributed Real-Time Applications.	IEEE Trans. Software Eng.	1999	DBLP DOI BibTeX RDF	Engineering of complex distributed real-time systems, integrated tool suites, user-transparent handling of complexity, runtime kernels, code transformers and optimizers, schedulability analyzers, compilation, C++, monitoring, debugging, allocation, CRL
12	Ramesh Karri, Kyosun Kim, Miodrag Potkonjak	Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Application specific programmable processors, fault tolerance, graceful degradation, behavioral synthesis
11	Ing-Jer Huang, Alvin M. Despain	Generating instruction sets and microarchitectures from applications.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Amin Asadi, Sarah G. Nurre Pinkley	A Monotone Approximate Dynamic Programming Approach for the Stochastic Scheduling, Allocation, and Inventory Replenishment Problem: Applications to Drone and Electric Vehicle Battery Swap Stations.	Transp. Sci.	2022	DBLP DOI BibTeX RDF
9	Kaan Gökcesu, Hakan Gökcesu	Efficient Locally Optimal Number Set Partitioning for Scheduling, Allocation and Fair Selection.	CoRR	2021	DBLP BibTeX RDF
9	Amin Asadi, Sarah G. Nurre Pinkley	A Monotone Approximate Dynamic Programming Approach for the Stochastic Scheduling, Allocation, and Inventory Replenishment Problem: Applications to Drone and Electric Vehicle Battery Swap Stations.	CoRR	2021	DBLP BibTeX RDF
9	Xabier Iturbe, Khaled Benkrid, Chuan Hong, Ali Ebrahim, Tughrul Arslan, Imanol Martinez	Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence.	Int. J. Reconfigurable Comput.	2013	DBLP DOI BibTeX RDF
9	Hariharan Sankaran, Srinivas Katkoori	Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
9	Anirban Sengupta, Reza Sedaghat	Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.	ISQED	2011	DBLP DOI BibTeX RDF
9	Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar, Summit Sehgal	Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications.	CCECE	2011	DBLP DOI BibTeX RDF
9	Karthik Lakshmanan, Dionisio de Niz, Ragunathan Rajkumar	Coordinated Task Scheduling, Allocation and Synchronization on Multiprocessors.	RTSS	2009	DBLP DOI BibTeX RDF
9	Hariharan Sankaran, Srinivas Katkoori	Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis.	ISVLSI	2008	DBLP DOI BibTeX RDF
9	Dongku Kang, Mark C. Johnson, Kaushik Roy 0001	Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.	ICCD	2003	DBLP DOI BibTeX RDF
9	José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba	Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.	DSD	2002	DBLP DOI BibTeX RDF
9	Gary William Grewal, Thomas Charles Wilson	An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.	Int. J. Comput. Intell. Appl.	2001	DBLP DOI BibTeX RDF
9	Alok Kumar, Anshul Kumar, M. Balakrishnan	Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs
9	Birger Landwehr, Peter Marwedel, Rainer Dömer	OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming.	EURO-DAC	1994	DBLP DOI BibTeX RDF
9	Thomas Charles Wilson, Gary William Grewal, Dilip K. Banerji	An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.	ICCD	1994	DBLP DOI BibTeX RDF
9	Richard J. Cloutier, Donald E. Thomas	The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm.	DAC	1990	DBLP DOI BibTeX RDF
6	Eunjoo Choi, Changsik Shin, Youngsoo Shin	ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
6	Xianwen Ke, Hao Zhou, Nan Jin, Xiaoxia Wan, Jianjun Zhao	Establishment of Containers Management System Based on RFID Technology.	CSSE (6)	2008	DBLP DOI BibTeX RDF
6	Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Palermo, Christian Pilato, Donatella Sciuto, Antonino Tumeo	An Evolutionary Approach to Area-Time Optimization of FPGA designs.	ICSAMOS	2007	DBLP DOI BibTeX RDF
6	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.	DATE	2006	DBLP DOI BibTeX RDF
6	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.	ISQED	2006	DBLP DOI BibTeX RDF
6	Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori	Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths.	ISVLSI	2005	DBLP DOI BibTeX RDF
6	Sune Fallgaard Nielsen, Jan Madsen	Power Constrained High-Level Synthesis of Battery Powered Digital Systems.	DATE	2003	DBLP DOI BibTeX RDF
6	Reinaldo A. Bergamaschi	Bridging the domains of high-level and logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
6	William E. Dougherty, Donald E. Thomas	Unifying behavioral synthesis and physical design.	DAC	2000	DBLP DOI BibTeX RDF	behavioral/high level synthesis, physical design
6	Yiorgos Makris, Alex Orailoglu	Channel-Based Behavioral Test Synthesis for Improved Module Reachability.	DATE	1999	DBLP DOI BibTeX RDF
6	Jonas Hallberg, Zebo Peng	Estimation and Consideration of Interconnection Delays during High-Level Synthesis.	EUROMICRO	1998	DBLP DOI BibTeX RDF
6	Shantanu Tarafdar, Miriam Leeser	The DT-Model: High-Level Synthesis Using Data Transfers.	DAC	1998	DBLP DOI BibTeX RDF	high-level synthesis, telecommunication
6	Catherine H. Gebotys	Throughput optimized architectural synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF