Search results for "Sense-Amplifiers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
70	Joseph F. Ryan 0002, Benton H. Calhoun	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.	ISQED	2008	DBLP DOI BibTeX RDF	Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
58	Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.	ASP-DAC	2001	DBLP DOI BibTeX RDF
42	Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang	New current-mode sense amplifiers for high density DRAM and PIM architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
40	Alexandre Ney, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	ETS	2007	DBLP DOI BibTeX RDF
40	Hong-Yi Huang, Shih-Lun Chen	Input isolated sense amplifiers.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
31	Aarti Choudhary, Sandip Kundu	A process variation tolerant self-compensating FinFET based sense amplifier design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	sense amplifier, robustness, process -variation, yield, sram, finfet
31	Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang	Variability Analysis for sub-100nm PD/SOI Sense-Amplifier.	ISQED	2008	DBLP DOI BibTeX RDF	PD/SOI, dopant fluctuation, sense amplifier, Variation
28	Byung-Do Yang, Lee-Sup Kim	A low power charge-recycling ROM architecture.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
25	Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne P. Burleson	Sensing Design Issues in Deep Submicron CMOS SRAMs.	ISVLSI	2005	DBLP DOI BibTeX RDF
21	Md. Mazharul Islam 0006, Shamiul Alam, Mohammad Adnan Jahangir, Garrett S. Rose, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta, Ahmedullah Aziz	Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing.	CoRR	2023	DBLP DOI BibTeX RDF
21	Christian D. Matthus, Frank Ellinger	Chopping for over 50 MHz gain-bandwidth product current sense amplifiers achieving input noise level of 8.5 nV/√Hz.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
21	Dae-Hyun Kim 0003, Byungkyu Song, Hyun-A. Ahn, Woongjoon Ko, Sung-Geun Do, Seokjin Cho, Kihan Kim, Seung-Hoon Oh, Hye-Yoon Joo, Geuntae Park, Jin-Hun Jang, Yong-Hun Kim, Donghun Lee, Jaehoon Jung, Yongmin Kwon, Youngjae Kim, Jaewoo Jung, Seongil O, Seoulmin Lee, Jaeseong Lim, Junho Son, Jisu Min, Haebin Do, Jaejun Yoon, Isak Hwang, Jinsol Park, Hong Shim, Seryeong Yoon, Dongyeong Choi, Jihoon Lee, Soohan Woo, Eunki Hong, Junha Choi, Jae-Sung Kim, Sangkeun Han, Jong-Min Bang, Bokgue Park, Jang-Hoo Kim, Seouk-Kyu Choi, Gong-Heum Han, Yoo-Chang Sung, Wonil Bae, Jeong-Don Lim, Seungjae Lee, Changsik Yoo, Sang Joon Hwang, Jooyoung Lee	A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process.	ISSCC	2022	DBLP DOI BibTeX RDF
21	Victor M. van Santen, Simon Thomann, Chaitanya Pasupuleti, Paul R. Genssler, Narendra Gangwar, Uma Sharma, Jörg Henkel, Souvik Mahapatra, Hussam Amrouch	BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array - including Sense Amplifiers and Write Drivers - under Processor Activity.	IRPS	2020	DBLP DOI BibTeX RDF
21	Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo, Mi-Young Kim, Min-Chul Shin, Seokjoon Kang, Junghyuk Yoon, Taek-Seung Kim, Seung-Tak Ryu	A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers.	IEEE J. Solid State Circuits	2019	DBLP DOI BibTeX RDF
21	Ivan Porin Tolic, Josip Mikulic, Gregor Schatzberger, Adrijan Baric	Design of Sense Amplifiers for Non-Volatile Memory.	MIPRO	2019	DBLP DOI BibTeX RDF
21	Alexandra Listl, Daniel Mueller-Gritschneder, Ulf Schlichtmann	MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs.	NEWCAS	2019	DBLP DOI BibTeX RDF
21	Manoj Sachdev	Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test.	SoCC	2019	DBLP DOI BibTeX RDF
21	Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas	Periodic Aging Monitoring in SRAM Sense Amplifiers.	IOLTS	2018	DBLP DOI BibTeX RDF
21	Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas	Aging monitoring in SRAM sense amplifiers.	MOCAST	2018	DBLP DOI BibTeX RDF
21	Zhiting Lin, Xiulong Wu, Zhi Li, Lijun Guan, Chunyu Peng, Changyong Liu, Junning Chen	A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
21	Mesut Atasoyu, Mustafa Altun, Serdar Özoguz, Kaushik Roy 0001	Spin-torque memristor based offset cancellation technique for sense amplifiers.	SMACD	2017	DBLP DOI BibTeX RDF
21	Soheil Salehi, Ronald F. DeMara	Process variation immune and energy aware sense amplifiers for resistive non-volatile memories.	ISCAS	2017	DBLP DOI BibTeX RDF
21	Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto	Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits.	AsianHOST	2016	DBLP DOI BibTeX RDF
21	Meng-Chou Chang, Siao-Siang Liu	FinFET-based TCAMs with matchline-accelerating sense amplifiers.	GCCE	2016	DBLP DOI BibTeX RDF
21	Samira Ataei, James E. Stine	Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
21	Mudit Bhargava, Kaship Sheikh, Ken Mai	Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers.	HOST	2015	DBLP DOI BibTeX RDF
21	Alireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram	Design optimization of sense amplifiers using deeply-scaled FinFET devices.	ISQED	2015	DBLP DOI BibTeX RDF
21	Mahmut E. Sinangil, Anantha P. Chandrakasan	Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
21	Taehui Na, Seung-Han Woo, Jisu Kim, Hanwool Jeong, Seong-Ook Jung	Comparative Study of Various Latch-Type Sense Amplifiers.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
21	Erulappan Sakthivel, Veluchamy Malathi, Muruganantham Arunraja	MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
21	Jianhui Wu, Jiafeng Zhu, YingCheng Xia, Na Bai	A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers.	IEEE Trans. Circuits Syst. II Express Briefs	2014	DBLP DOI BibTeX RDF
21	Meng-Chou Chang, Shih-Ju Tsai	A low-power ternary content-addressable memory using pulse current based match-line sense amplifiers.	ASICON	2013	DBLP DOI BibTeX RDF
21	Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Aida Todri, Arnaud Virazel, Nabil Badereddine	Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures.	DTIS	2013	DBLP DOI BibTeX RDF
21	Sherif M. Sharroush, Yasser S. Abdalla, Ahmed A. Dessouki, El-Sayed A. El-Badawy	Dynamic random-access memories without sense amplifiers.	Elektrotech. Informationstechnik	2012	DBLP DOI BibTeX RDF
21	Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe	A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
21	Michael Wieckowski, Gregory K. Chen, Daeyeon Kim, David T. Blaauw, Dennis Sylvester	A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers.	ISQED	2011	DBLP DOI BibTeX RDF
21	Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe	A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
21	S. H. Woo, H. Kang, K. Park, S.-O. Jung	Offset voltage estimation model for latch-type sense amplifiers.	IET Circuits Devices Syst.	2010	DBLP DOI BibTeX RDF
21	Stefan Cosemans, Wim Dehaene, Francky Catthoor	A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
21	Alexandre Ney, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
21	Shinya Kajiyama, Masamichi Fujito, Hideo Kasai, Makoto Mizuno, Takanori Yamaguchi, Yutaka Shinagawa	A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
21	Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev	A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
21	Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai	Low-overhead, digital offset compensated, SRAM sense amplifiers.	CICC	2009	DBLP DOI BibTeX RDF
21	Piotr Nasalski, Adam Makosiej, Bastien Giraud, Andrei Vladimirescu, Amara Amara	SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch.	ISCAS	2009	DBLP DOI BibTeX RDF
21	Anh-Tuan Do, Zhi-Hui Kong, Kiat Seng Yeo	Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
21	Stefan Cosemans, Wim Dehaene, Francky Catthoor	A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability.	ESSCIRC	2008	DBLP DOI BibTeX RDF
21	Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev	Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories.	CICC	2006	DBLP DOI BibTeX RDF
21	Riichiro Takemura, Kiyoo Itoh 0001, Tomonori Sekiguchi	A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers.	ISLPED	2006	DBLP DOI BibTeX RDF	FD-SOI, dynamic-VT sense amplifier, low-voltage RAM, twin-cell DRAM
21	Byung-Do Yang, Lee-Sup Kim	A low-power SRAM using hierarchical bit line and local sense amplifiers.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
21	R. Singh, N. Bhat	An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
21	Jörg E. Vollrath	Signal Margin Analysis for Memory Sense Amplifiers .	DELTA	2002	DBLP DOI BibTeX RDF	Signal margin, Test, Memory, Diagnosis, DRAM
21	Bernhard Wicht, Steffen Paul, Doris Schmitt-Landsiedel	Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
21	Jente B. Kuang, David H. Allen, Ching-Te Chuang	Dynamic body charge modulation for sense amplifiers in partially depleted SOI technology.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
21	Osamu Takahashi, Naoaki Aoki, Joel Silberman, Sang H. Dhong	A 1-GHz logic circuit family with sense amplifiers.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
21	Marco Pasotti, Pier Luigi Rolandi, Roberto Canegallo, Danilo Gerna, Giovanni Guaitini, Frank Lhermet, Alan Kramer	Analog sense amplifiers for high density NOR flash memories.	CICC	1999	DBLP DOI BibTeX RDF
21	Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida	A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
21	Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki	A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
21	Gerson H. Goldstick, Edmund F. Klein	Design of Memory Sense Amplifiers.	IRE Trans. Electron. Comput.	1962	DBLP DOI BibTeX RDF
19	Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella	Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns.	HiPC	2006	DBLP DOI BibTeX RDF
19	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	logic synthesis, PLA
16	Yan Li 0030, Helmut Schneider, Florian Schnabel 0002, Roland Thewes, Doris Schmitt-Landsiedel	Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization.	PATMOS	2008	DBLP DOI BibTeX RDF
16	Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
16	Raymond A. Heald, Ping Wang	Variability in sub-100nm SRAM designs.	ICCAD	2004	DBLP DOI BibTeX RDF
16	Sandro A. P. Haddad, Sebastian Gieltjes, Richard Houben, Wouter A. Serdijn	An ultra low-power dynamic translinear cardiac sense amplifier for pacemakers.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
16	Caroline Papaix, Jean Michel Daga	A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories.	MTDT	2002	DBLP DOI BibTeX RDF
16	Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Energy recovering static memory.	ISLPED	2002	DBLP DOI BibTeX RDF	adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design
12	Ling Zhang, Yulei Zhang 0002, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng	High performance on-chip differential signaling using passive compensation for global communication.	ASP-DAC	2009	DBLP DOI BibTeX RDF
12	Major Bhadauria, Sally A. McKee	Optimizing thread throughput for multithreaded workloads on memory constrained CMPs.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	performance, efficiency, power, memory bandwidth
12	Shruti R. Patil, Xiaofeng Yao, Hao Meng, Jianping Wang, David J. Lilja	Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	alu design, magnetic tunnel junction, spintronic alu design, spintronics
12	Kiyoo Itoh 0001, Masanao Yamaoka, Takayuki Kawahara	Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	FD-SOI, VT variation, bulk, deep-sub-100-nm CMOS LSIs, minimum VDD, speed variation, leakage, SRAM, DRAM, logic gate
12	Suwen Yang, Mark R. Greenstreet	Simulating Improbable Events.	DAC	2007	DBLP DOI BibTeX RDF
12	Kaushik Roy 0001, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici	Double-Gate SOI Devices for Low-Power and High-Performance Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
12	Nam Sung Kim, David T. Blaauw, Trevor N. Mudge	Quantitative analysis and optimization techniques for on-chip cache leakage power.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
12	Bruce F. Cockburn, Jesús Hernández Tapia, Duncan G. Elliott	A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing.	MTDT	2003	DBLP DOI BibTeX RDF
12	Mario R. Casu, Philippe Flatresse	Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.	MTDT	2002	DBLP DOI BibTeX RDF
12	Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada	Logic synthesis for PLA with 2-input logic elements.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
12	Norio Kuji	Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	Electron beam testers, Guided-probe diagnosis, Memory-macro cells, Logic-behavior models, Logic simulation