Search results for "Spartan-3"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
53	Dirk Koch, Christian Beckhoff, Jürgen Teich	A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, reconfiguration, communication architecture
53	Enrique Cantó, Francesc Fons, Mariano López	Self-recofigurable embedded systems on Spartan-3.	FPL	2008	DBLP DOI BibTeX RDF
36	Thuong Le-Tien, Dien Vo-Ngoc, Lan Ngo-Hoang, Sungyoung Lee	Independent Component Analysis Applied to Watermark Extraction and its Implemented Model on FPGAs.	DELTA	2010	DBLP DOI BibTeX RDF	Psychoacoustic masking, Spartan-3, FPGA, ICA, Audio watermarking, LSB
29	Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Angel Jiménez-Fernandez, Tobi Delbrück, P. Lichtensteiner	Using FPGA for visuo-motor control with a silicon retina and a humanoid robot.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Corina Savulescu, Mariana Iorgulescu	The implementation of Hamming decoder on Spartan 3.	ECAI	2014	DBLP DOI BibTeX RDF
24	Enrique Cantó, Mariano Fons, Francesc Fons, Mariano López, Rafael Ramos-Lara	Fast Self-Reconfigurable Embedded System on Spartan-3.	J. Univers. Comput. Sci.	2013	DBLP DOI BibTeX RDF
24	Michael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth, Jürgen Becker 0001	Addiguration: Exploring configuration behavior of Spartan-3 devices.	ReCoSoC	2013	DBLP DOI BibTeX RDF
24	Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001	Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems.	Microprocess. Microsystems	2009	DBLP DOI BibTeX RDF
24	Enrique Cantó, Mariano Fons, Mariano López-García, Rafael Ramos-Lara	Acceleration of complex algorithms on a fast reconfigurable embedded system on Spartan-3.	FPL	2009	DBLP DOI BibTeX RDF
24	Katarina Paulsson, Ulrich Viereck, Michael Hübner 0001, Jürgen Becker 0001	Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs.	ISVLSI	2008	DBLP DOI BibTeX RDF
15	Shantanu Dutt, Li Li	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes
15	Karl Papadantonakis, Nachiket Kapre, Stephanie Chan, André DeHon	Pipelining Saturated Accumulation.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
15	Alejandro Linares-Barranco, Rafael Paz, Francisco Gomez-Rodriguez, Angel Jiménez-Fernandez, Manuel Rivas, Gabriel Jiménez, Antón Civit	FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems.	IWANN (1)	2009	DBLP DOI BibTeX RDF
15	Young H. Cho, William H. Mangione-Smith	Deep network packet filter design for reconfigurable devices.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	string filter, Firewall, worm, network intrusion detection, virus
15	Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle	Radio frequency identification prototyping.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	low-power, RFID, prototyping, Design automation
15	Jose de Jesus Rangel-Magdaleno, René de Jesús Romero-Troncoso, Luis Miguel Contreras-Medina, Arturo Garcia-Perez	FPGA implementation of a novel algorithm for on-line bar breakage detection on induction motors.	FPGA	2008	DBLP DOI BibTeX RDF	bar breakage, FPGA, embedded systems
15	Angel Jiménez-Fernandez, Rafael Paz-Vicente, Manuel Rivas, Alejandro Linares-Barranco, Gabriel Jiménez, Antón Civit	AER-based robotic closed-loop control system.	ISCAS	2008	DBLP DOI BibTeX RDF
15	Iván González 0004, Estanislao Aguayo, Sergio López-Buedo	Self-Reconfigurable Embedded Systems on Low-Cost FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	reconfigurable hardware, real-time and embedded systems, special-purpose and application-based systems, algorithms implemented in hardware
15	Pavel Zaykov	MIMD implementation with PicoBlaze microprocessor using MPI functions.	CompSysTech	2007	DBLP DOI BibTeX RDF	MPI functions, PicoBlaze, FPGA, system-on-chip, VHDL, MIMD, parallel computer architecture, message passing system
15	Christoforos Kachris, Chidamber Kulkarni	Configurable Transactional Memory.	FCCM	2007	DBLP DOI BibTeX RDF
15	Chris Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang	Low-Cost Stereo Vision on an FPGA.	FCCM	2007	DBLP DOI BibTeX RDF
15	Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria	A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona	LVDS Serial AER Link performance.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
15	Jeffrey William Schuster, Kshitij Gupta, Raymond R. Hoare	Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition.	IPDPS	2006	DBLP DOI BibTeX RDF
15	Hui Qin, Tsutomu Sasao, Jon T. Butler	Implementation of LPM Address Generators on FPGAs.	ARC	2006	DBLP DOI BibTeX RDF
15	Wei-Tsen Lin, Dah-Chung Chang	The extended Kalman filtering algorithm for carrier synchronization and the implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi	Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware.	CHES	2006	DBLP DOI BibTeX RDF	Cipher-breaking, FPGA, factoring, ECM
15	Vijay Degalahal, Tim Tuan	Methodology for high level estimation of FPGA power consumption.	ASP-DAC	2005	DBLP DOI BibTeX RDF
15	Paul Baker, Tim Todman, Henry Styles, Wayne Luk	Reconfigurable Designs for Radiosity.	FCCM	2005	DBLP DOI BibTeX RDF
15	Mounir Boukadoum, Karima Tabari, Abdelhak Bensaoula, David Starikov, El Mostapha Aboulhamid	FPGA implementation of a CDMA source coding and modulation subsystem for a multiband fluorometer with pattern recognition capabilities.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
15	Young H. Cho, William H. Mangione-Smith	Deep Packet Filter with Dedicated Logic and Read Only Memories.	FCCM	2004	DBLP DOI BibTeX RDF
15	Erik Chmelar	Minimizing the number of test configurations for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
15	Xizhi Li, Tiecai Li	ECOMIPS: An Economic MIPS CPU Design on FPGA.	IWSOC	2004	DBLP DOI BibTeX RDF