Search results for "Synopsys"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
57		Power Management in Synopsys Galaxy Design Platform.	PATMOS	2003	DBLP DOI BibTeX RDF
54	Nainesh Agarwal, Nikitas J. Dimopoulos	Efficient Automated Clock Gating Using CoDeL.	SAMOS	2006	DBLP DOI BibTeX RDF
50	Nam Ling, Rajesh Advani	Architecture of a fast motion estimator for MPEG video coding.	ISPAN	1996	DBLP DOI BibTeX RDF	fast motion estimator, MPEG video coding, 2-D log search, MPEG2 video, motion estimation, motion estimator, video coding, systolic arrays, motion vector, Verilog, Synopsys
41	Nainesh Agarwal, Nikitas J. Dimopoulos	DSPstone Benchmark of CoDeL's Automated Clock Gating Platform.	ISVLSI	2007	DBLP DOI BibTeX RDF
41	Pierre Bricaud	VC Rating and Quality Metrics: Why Bother?	ISQED	2002	DBLP DOI BibTeX RDF
30	Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera	Supplemental PDK for ASAP7 Using Synopsys Flow.	IPSJ Trans. Syst. LSI Des. Methodol.	2021	DBLP DOI BibTeX RDF
30	Yongfu Li 0003, Wan Chia Ang, Chin Hui Lee, Kok Peng Chua, Yoong Seang Jonathan Ong, Chiu Wing Colin Hui	Standard Cell Library Evaluation with Multiple lithography-compliant verification and Improved Synopsys Pin Access Checking Utility.	CoRR	2018	DBLP BibTeX RDF
30	Yongfu Li 0003, Chin Hui Lee, Wan Chia Ang, Kok Peng Chua, Yoong Seang Jonathan Ong, Chiu Wing Colin Hui	Constraining the Synopsys Pin Access Checker Utility for Improved Standard Cells Library Verification Flow.	CoRR	2018	DBLP BibTeX RDF
30	I-Lun Tseng, Valerio Perez, Yongfu Li 0003, Zhao Chuan Lee, Vikas Tripathi, Yoong Seang Jonathan Ong	Creation and Fixing of Lithography Hotspots with Synopsys Tools.	CoRR	2018	DBLP BibTeX RDF
30	Enrico Ghillino, Emanuele Virgillito, Pablo V. Mena, Rob Scarmozzino, Remco Stoffer, Dwight H. Richards, Ali Ghiasi, Alessio Ferrari 0002, Mattia Cantono, Andrea Carena, Vittorio Curri	The Synopsys Software Environment to Design and Simulate Photonic Integrated Circuits: A Case Study for 400G Transmission.	ICTON	2018	DBLP DOI BibTeX RDF
30	Yao-Ming Kuo, Leandro J. Arana, Luis Seva, Cristian Marchese, Leandro Tozzi	Educational design kit for synopsys tools with a set of characterized standard cell library.	LASCAS	2018	DBLP DOI BibTeX RDF
30	Tim Kogel	Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
30	Danila A. Gorodecky	Multipliers: comparison of Fourier transformation based method and Synopsys design technique for up to 32 bits inputs in regular and saturation arithmetics.	CoRR	2016	DBLP BibTeX RDF
30	Michael Rudolf 0001, Hannes Voigt, Christof Bornhövd, Wolfgang Lehner	SynopSys: Foundations for Multidimensional Graph Analytics.	BIRTE	2014	DBLP DOI BibTeX RDF
30	Richard Goldman, Karen Bartleson, Troy Wood, Vazgen Melikyan, Eduard Babayan	Synopsys' Educational Generic Memory Compiler.	EWME	2014	DBLP DOI BibTeX RDF
30	Tri Caohuu, John Edwards	Implementation of an Efficient Library for Asynchronous Circuit Design with Synopsys.	ICSEng	2014	DBLP DOI BibTeX RDF
30	Nana Sutisna, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi	Live demonstration: Hardware-software co-verification for very large scale SoC using synopsys HAPS platform.	APCCAS	2014	DBLP DOI BibTeX RDF
30	N. L. Lagunovich, V. M. Borzdov, Arkady Turtsevich	Simulation features of diffusion doping process by means of software package of synopsys company.	EWDTS	2013	DBLP DOI BibTeX RDF
30	Michael Rudolf 0001, Marcus Paradies, Christof Bornhövd, Wolfgang Lehner	SynopSys: large graph analytics in the SAP HANA database through summarization. (PDF / PS)	GRADES	2013	DBLP DOI BibTeX RDF
30	Prakash Shanbhag, Chandramouli Gopalakrishnan, Saibal Ghosh	A Case Study in Developing an Efficient Multi-threaded EDA Parser: Synopsys SDF Parser.	ISVLSI	2012	DBLP DOI BibTeX RDF
30	Jianchao Lu, Baris Taskin	From RTL to GDSII: An ASIC design course development using Synopsys® University Program.	MSE	2011	DBLP DOI BibTeX RDF
30	Richard Goldman, Karen Bartleson, Troy Wood, Kevin Kranen, C. Cao, Vazgen Melikyan, Gayane Markosyan	Synopsys' open educational design kit: Capabilities, deployment and future.	MSE	2009	DBLP DOI BibTeX RDF
30	Eli Lyons, Vish Ganti, Richard Goldman, Vazgen Melikyan, Hamid Mahmoodi	Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library.	MSE	2009	DBLP DOI BibTeX RDF
30	Vishy Lakshmanan	Automated Fixing of Complex/Process Critical DRC Violations in Place and Route Systems Using Calibre in the Synopsys/Milkyway Environment.	IWSOC	2004	DBLP DOI BibTeX RDF
30	Peter Blinzer, Ulrich Golze, Ulrich Holtmann	Entwurf von Controller-Schaltungen für Kommunikationsprotokolle mit dem Protocol-Compiler von Synopsys.	MBMV	1998	DBLP BibTeX RDF
30	R. Picchiottino, G. Georgoulis, G. Sicouri, Annick Panaye, Jacques-Emile Dubois	DARC-SYNOPSYS. Designing specific reaction data banks: application to KETO-REACT.	J. Chem. Inf. Comput. Sci.	1984	DBLP DOI BibTeX RDF
27	Jonathan Young	Capturing and Analyzing IC Design Productivity Metrics.	DATE	2008	DBLP DOI BibTeX RDF
27	Ankur Srivastava 0001, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh	Achieving Design Closure Through Delay Relaxation Parameter.	ICCAD	2003	DBLP DOI BibTeX RDF
27	Jovanka Ciric, Gin Yee, Carl Sechen	Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic.	DATE	2000	DBLP DOI BibTeX RDF
14	Olivier Coudert	An efficient algorithm to verify generalized false paths.	DAC	2010	DBLP DOI BibTeX RDF	co-sensitization, generalized false path, timing exception, formal verification, correctness, SAT, sensitization, false path, SDC
14	Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis	Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Coarse-grained reconfigurable arrays, High productivity tools, Modulo scheduling, Architectural exploration, Compiler techniques
14	Rajdeep Mukhopadhyay, Subrat Kumar Panda, Pallab Dasgupta, John Gough	Instrumenting AMS assertion verification on commercial platforms.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	OVL, SVA, integrated mixed signal design, verification library, simulation, Assertion
14	Jinsil Kim, Wonyoung Chung, Junghee Lee, Yongsurk Lee	An implementation of the CQS supporting multimedia traffic.	ICHIT	2009	DBLP DOI BibTeX RDF	CQS, dequeue, enqueue, scheduler
14	Mohammad-Hamed Razmkhah, Seyed Ghassem Miremadi, Alireza Ejlali	A Micro-FT-UART for Safety-Critical SoC-Based Applications.	ARES	2009	DBLP DOI BibTeX RDF
14	M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig	Design of a low power MPEG-1 motion vector reconstructor.	SBCCI	2009	DBLP DOI BibTeX RDF	behavioural synthesis, low power
14	Shanq-Jang Ruan, Chi-Yu Wu, Jui-Yuan Hsieh	Low Power Design of Precomputation-Based Content-Addressable Memory.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
14	Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew	GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
14	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
14	Chun-Lung Hsu, Yu-Sheng Huang	A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter
14	Frank Badstubner, Andreas Vörg	Quantitative Productivity Measurement in IC Design.	DATE	2008	DBLP DOI BibTeX RDF
14	Jui-Yuan Hsieh, Shanq-Jang Ruan	Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Yi Zhu 0002, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng	Timing-power optimization for mixed-radix Ling adders by integer linear programming.	ASP-DAC	2008	DBLP DOI BibTeX RDF
14	Antun Domic	Design or manufacturing: which will be best for the future of the semiconductor roadmap?	ISPD	2008	DBLP DOI BibTeX RDF
14	Alain Pegatoquet, Filip Thoen, Denis Paterson	Virtual Reality for 2.5 G Wireless Communication Modem Software Development.	COMPSAC	2008	DBLP DOI BibTeX RDF	EGPRS, simulation, MPSoC, GSM, GPRS, Virtual platform
14	Deepak Sreedharan, Ali Akoglu	A hybrid processing element based reconfigurable architecture for hashing algorithms.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Azam Beg, P. W. Chandana Prasad, Walid Ibrahim, Emad Abu Shama	Utilizing synthesis to verify Boolean function models.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin	An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches.	ISCAS	2008	DBLP DOI BibTeX RDF
14	Somayyeh Koohi, Mohammad Mirza-Aghatabar, Shaahin Hessabi, Massoud Pedram	High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.	VLSI Design	2008	DBLP DOI BibTeX RDF
14	Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang	Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol.	FGCN (2)	2007	DBLP DOI BibTeX RDF
14	Noureddine Chabini, Wayne H. Wolf	Register binding guided by the size of variables.	ICCD	2007	DBLP DOI BibTeX RDF
14	Makoto Ishikawa, D. J. McCune, George Saikalis, Shigeru Oho	CPU Model-Based Hardware/Software Co-design, Co-simulation and Analysis Technology for Real-Time Embedded Control Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2007	DBLP DOI BibTeX RDF
14	Jimson Mathew, Hafizur Rahaman 0001, Dhiraj K. Pradhan	Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set.	IOLTS	2007	DBLP DOI BibTeX RDF
14	Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong	A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD.	ICEC	2007	DBLP DOI BibTeX RDF	Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur
14	Tianmiao Wang, Kai Sun, Hongxing Wei, Meng Wang 0005, Zili Shao, Hui Liu 0006	Interconnection Synthesis of MPSoC Architecture for Gamma Cameras.	EUC	2007	DBLP DOI BibTeX RDF
14	Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong	An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.	MMM (2)	2007	DBLP DOI BibTeX RDF	VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm
14	Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi	A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.	PRDC	2007	DBLP DOI BibTeX RDF	SEU-Tolerance, Power Consumption, NoC
14	Nikhil Bansal 0003, Kanishka Lahiri, Anand Raghunathan	Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji	Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
14	Raghavendra Rao Loka	Compilation reuse and hybrid compilation: an experiment.	ACM SIGPLAN Notices	2006	DBLP DOI BibTeX RDF
14	M. Capobianchi, V. Labay, F. Shi, G. Mizushima	Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Kaijie Wu 0001, Ramesh Karri	Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
14	Salvatore Carta, Danilo Pani, Luigi Raffo	Reconfigurable Coprocessor for Multimedia Application Domain.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	multimedia, reconfigurable computing, digital signal processing, domain-specific architectures
14	Sau-Gee Chen, Jen-Chuan Chih, Jun-Yi Chou	Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	direct digital frequency synthesizer, DDFS algorithm, two-level table lookup scheme
14	Flavio M. de Paula, Alan J. Hu	EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation.	CAV	2006	DBLP DOI BibTeX RDF
14	Sandro Penolazzi, Axel Jantsch	A High Level Power Model for the Nostrum NoC.	DSD	2006	DBLP DOI BibTeX RDF
14	Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto	An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC.	ISVC (2)	2006	DBLP DOI BibTeX RDF
14	Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew	An efficient technique for synthesis and optimization of polynomials in GF(2m).	ICCAD	2006	DBLP DOI BibTeX RDF
14	Itai Yarom, Viji Patil	Smart-Lint: Improving the Verification Flow.	Haifa Verification Conference	2006	DBLP DOI BibTeX RDF
14	Rong-Jian Chen, Yi-Te Lai, Jui-Lin Lai	Architecture design and VLSI hardware implementation of image encryption/decryption system using re-configurable 2D Von Neumann cellular automata.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Sizhong Chen, Tong Zhang 0002, Manish Goel	Relaxed tree search MIMO signal detection algorithm design and VLSI implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Nainesh Agarwal, Nikitas J. Dimopoulos	Power efficient rapid hardware development using CoDel and automated clock gating.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Fei Sun, Tong Zhang 0002	Low power state-parallel relaxed adaptive Viterbi decoder design and implementation.	ISCAS	2006	DBLP DOI BibTeX RDF
14	Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking and Code-Disjoint Non-Restoring Array Divider.	IOLTS	2006	DBLP DOI BibTeX RDF
14	Lun Li, Mitchell A. Thornton, David W. Matula	A digit serial algorithm for the integer power operation.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	power operation, standard cell implementation, exponential, discrete log
14	Darshana Patel, Radu Muresan	Triple-DES ASIC Module for a Power-Smart System-on-Chip Architecture.	CCECE	2006	DBLP DOI BibTeX RDF
14	Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu	Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits.	PRDC	2006	DBLP DOI BibTeX RDF
14	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
14	Ankur Srivastava 0001, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh	On effective slack management in postscheduling phase.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
14	Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong	IR Drop and Ground Bounce Awareness Timing Model.	ISVLSI	2005	DBLP DOI BibTeX RDF
14	Wayne P. Burleson, Sheng Xu	Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats.	MSE	2005	DBLP DOI BibTeX RDF
14	James E. Stine, Johannes Grad, Ivan D. Castellanos, Jeff M. Blank, Vibhuti B. Dave, Mallika Prakash, Nick Iliev, Nathan Jachimiec	A Framework for High-Level Synthesis of System-on-Chip Designs.	MSE	2005	DBLP DOI BibTeX RDF
14	Dae-Sung Ku, Jung-Hyun Yun, Jong-Bin Kim	A Design on the Vector Processor of 2048point MDCT/IMDCT for MPEG-2 AAC.	ICNC (3)	2005	DBLP DOI BibTeX RDF
14	Ravi Kumar Satzoda, Chip-Hong Chang	VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
14	Rong-Jian Chen, Yi-Te Lai, Jui-Lin Lai	Architecture design of the re-configurable 2-D von Neumann cellular automata for image encryption application.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
14	Rui Tang, Fengming Zhang, Yong-Bin Kim	QCA-based nano circuits design [adder design example].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen	An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
14	Saraju P. Mohanty, N. Ranganathan, Karthikeyan Balakrishnan	Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.	VLSI Design	2005	DBLP DOI BibTeX RDF
14	Kaijie Wu 0001, Ramesh Karri	Fault secure datapath synthesis using hybrid time and hardware redundancy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
14	Shuo Sheng, Michael S. Hsiao	Success-Driven Learning in ATPG for Preimage Computation.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
14	Serdar Tasiran, Yuan Yu, Brannon Batson	Linking Simulation with Formal Verification at a Higher Level.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
14	Martin Zambaldi, Wolfgang Ecker, Renate Henftling, Matthias Bauer 0003	A Layered Adaptive Verification Platform for Simulation, Test, and Emulation.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
14	Bin Sheng, Wen Gao 0001, Di Wu 0022	An implemented architecture of deblocking filter for H.264/AVC.	ICIP	2004	DBLP DOI BibTeX RDF
14	Carl Pixley, D. Meyers, S. McMaster, A. Chittor	Designers want proofs - but show me the money.	MEMOCODE	2004	DBLP DOI BibTeX RDF
14	Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.	DATE	2004	DBLP DOI BibTeX RDF
14	Juan C. Diaz, Marta Saburit	Clock Management in a Gigabit Ethernet Physical Layer Transceiver Circuit.	DATE	2004	DBLP DOI BibTeX RDF
14	Donna Nakano, Erric Solomon	Task oriented visual interface for debugging timing problems in hardware design.	AVI	2004	DBLP DOI BibTeX RDF	cognitive model of users, information visualization, visual interface design
14	Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin	Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors.	PRDC	2004	DBLP DOI BibTeX RDF
14	Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines	EDA: this is serious business.	DAC	2004	DBLP DOI BibTeX RDF
14	Ravi Hosabettu, Ganesh Gopalakrishnan, Mandayam K. Srivas	A Practical Methodology for Verifying Pipelined Microarchitectures.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
14	Hunsoo Choo, Khurram Muhammad, Kaushik Roy 0001	MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.	DATE	2003	DBLP DOI BibTeX RDF