Search results for "TILE64"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
71	Xuan-Yi Lin, Kuan-Chou Lai, Shau-Yin Tseng, Kuan-Ching Li, Yeh-Ching Chung	An Efficient Programming Paradigm for Shared-Memory Master-Worker Video Decoding on TILE64 Many-Core Platform.	ICPP	2011	DBLP DOI BibTeX RDF	producer-consumer, TILE64, shared memory, programming paradigm, many-core, master-worker
34	Hamdi Ayed, Jean-Luc Scharbarg, Jérôme Ermont, Christian Fraboul	Extended recursive analysis for tilera tile64 NoC architectures: towards inter-NoC delay analysis.	SIGBED Rev.	2017	DBLP DOI BibTeX RDF
34	Myriam Kurtz, Francisco José Esteban 0002, Pilar Hernández, Juan Antonio Caballero, Antonio Guevara, Gabriel Dorado, Sergio Gálvez	Bioinformatics Performance Comparison of Many-core Tile64 vs. Multi-core Intel Xeon.	CLEI Electron. J.	2014	DBLP DOI BibTeX RDF
34	Xuan-Yi Lin, Yeh-Ching Chung	Master-worker model for MapReduce paradigm on the TILE64 many-core platform.	Future Gener. Comput. Syst.	2014	DBLP DOI BibTeX RDF
34	Chien-Wei Chen, Yi-Ta Wu, Shau-Yin Tseng, Wen-Shan Wang	Parallelization of Connected-Component Labeling on TILE64 Many-Core Platform.	J. Signal Process. Syst.	2014	DBLP DOI BibTeX RDF
34	Xuan-Yi Lin, Kuan-Chou Lai, Kuan-Ching Li, Yeh-Ching Chung	Efficient programming paradigm for video streaming processing on TILE64 platform.	J. Supercomput.	2013	DBLP DOI BibTeX RDF
34	Chenggang Yan 0001, Feng Dai, Yongdong Zhang 0001, Yike Ma, Licheng Chen, Lingjun Fan, Yasong Zheng	Parallel deblocking filter for H.264/AVC implemented on Tile64 platform.	ICME	2011	DBLP DOI BibTeX RDF
34	Xuan-Yi Lin, Chung-Yu Huang, Pei-Man Yang, Tai-Wen Lung, Shau-Yin Tseng, Yeh-Ching Chung	Parallelization of Motion JPEG Decoder on TILE64 Many-Core Platform.	MTPP	2010	DBLP DOI BibTeX RDF
34	Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce, Vince Leung, John MacKay, Mike Reif, Liewei Bao, John F. Brown III, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, John Zook	TILE64 - Processor: A 64-Core SoC with Mesh Interconnect.	ISSCC	2008	DBLP DOI BibTeX RDF
26	Jungwoo Ha, Stephen P. Crago	Opportunities for concurrent dynamic analysis with explicit inter-core communication.	PASTE	2010	DBLP DOI BibTeX RDF	inter-core communication, concurrency, dynamic analysis, instrumentation
26	Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng	NTPT: on the end-to-end traffic prediction in the on-chip networks.	DAC	2010	DBLP DOI BibTeX RDF	end-to-end traffic prediction, network-on-chip, many-core
26	William Lundgren	Gedae's automated management of hierarchical memories on multicore processors Commercial Tutorial.	IPDPS	2008	DBLP DOI BibTeX RDF
26	David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, Anant Agarwal	On-Chip Interconnection Architecture of the Tile Processor.	IEEE Micro	2007	DBLP DOI BibTeX RDF	MIMD processors, parallel architectures, mesh networks, multicore architectures, on-chip interconnection networks