Search results for "TLBs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
112	Qidong Xu, Patricia J. Teller	Unified vs. split TLBs and caches in shared-memory MP systems.	IPPS	1995	DBLP DOI BibTeX RDF	data references, performance evaluation, caches, discrete event simulation, shared-memory multiprocessors, shared memory systems, trace-driven simulations, cache storage, performance gains, translation-lookaside buffer
111	Aamer Jaleel, Bruce L. Jacob	In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts
67	André Seznec	Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	multiple page size, skewed associativity, TLB
51	Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic	Synonymous address compaction for energy reduction in data TLB.	ISLPED	2005	DBLP DOI BibTeX RDF	low-power TLB, spatial and temporal locality, multi-porting
51	Gokul B. Kandiraju, Anand Sivasubramaniam	Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
51	Madhusudhan Talluri, Mark D. Hill	Surpassing the TLB Performance of Superpages with Less Operating System Support.	ASPLOS	1994	DBLP DOI BibTeX RDF
45	Emre Özer 0001, Stuart Biles	Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
45	Richard Uhlig, David Nagle, Timothy J. Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown	Design Tradeoffs for Software-Managed TLBs.	ACM Trans. Comput. Syst.	1994	DBLP DOI BibTeX RDF	translation lookaside buffer (TLB), trap-driven simulation, hardware monitoring
34	Yen-Jen Chang	An ultra low-power TLB design.	DATE	2006	DBLP DOI BibTeX RDF
34	Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman	Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.	ISQED	2005	DBLP DOI BibTeX RDF
34	Magnus Ekman, Per Stenström, Fredrik Dahlgren	TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF	virtual caches, low-power, CMP, snoop
34	Adam Wiggins, Gernot Heiser	Fast Address-Space Switching on the StrongARM SA-1100 Processor.	ACAC	2000	DBLP DOI BibTeX RDF
33	Richard Uhlig, Trevor N. Mudge	Trace-Driven Memory Simulation: A Survey.	ACM Comput. Surv.	1997	DBLP DOI BibTeX RDF	memory simulation, caches, memory management, trace-driven simulation, TLBs
28	Bin Gao, Qingxuan Kang, Hao-Wei Tee, Kyle Timothy Ng Chu, Alireza Sanaee, Djordje Jevdjic	numaPTE: Managing Page-Tables and TLBs on NUMA Systems.	CoRR	2024	DBLP DOI BibTeX RDF
28	Shuwen Deng, Wenjie Xiong 0001, Jakub Szefer	Designing Secure TLBs.	IEEE Des. Test	2024	DBLP DOI BibTeX RDF
28	Florian Stolz, Jan Philipp Thoma, Pascal Sasdrich, Tim Güneysu	Risky Translations: Securing TLBs against Timing Side Channels.	IACR Trans. Cryptogr. Hardw. Embed. Syst.	2023	DBLP DOI BibTeX RDF
28	Zhenkai Zhang, Tyler N. Allen, Fan Yao, Xing Gao 0001, Rong Ge 0002	TunneLs for Bootlegging: Fully Reverse-Engineering GPU TLBs for Challenging Isolation Guarantees of NVIDIA MIG.	CCS	2023	DBLP DOI BibTeX RDF
28	Florian Stolz, Jan Philipp Thoma, Pascal Sasdrich, Tim Güneysu	Risky Translations: Securing TLBs against Timing Side Channels.	IACR Cryptol. ePrint Arch.	2022	DBLP BibTeX RDF
28	Chao Yu 0001, Yuebin Bai, Rui Wang 0014	Enabling Large-Reach TLBs for High-Throughput Processors by Exploiting Memory Subregion Contiguity.	CoRR	2021	DBLP BibTeX RDF
28	Chandrashis Mazumdar, Prachatos Mitra, Arkaprava Basu	Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together.	HPCA	2021	DBLP DOI BibTeX RDF
28	Steffen Maass, Mohan Kumar Kumar, Taesoo Kim, Tushar Krishna, Abhishek Bhattacharjee	ECOTLB: Eventually Consistent TLBs.	ACM Trans. Archit. Code Optim.	2020	DBLP DOI BibTeX RDF
28	Jakob Koschel, Cristiano Giuffrida, Herbert Bos, Kaveh Razavi	TagBleed: Breaking KASLR on the Isolated Kernel Address Space using Tagged TLBs.	EuroS&P	2020	DBLP DOI BibTeX RDF
28	Hussein Elnawawy, Rangeen Basu Roy Chowdhury, Amro Awad, Gregory T. Byrd	Diligent TLBs: a mechanism for exploiting heterogeneity in TLB miss behavior.	ICS	2019	DBLP DOI BibTeX RDF
28	Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee	Translation ranger: operating system support for contiguity-aware TLBs.	ISCA	2019	DBLP DOI BibTeX RDF
28	Shuwen Deng, Wenjie Xiong 0001, Jakub Szefer	Secure TLBs.	ISCA	2019	DBLP DOI BibTeX RDF
28	Srikant Bharadwaj, Guilherme Cox, Tushar Krishna, Abhishek Bhattacharjee	Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects.	MICRO	2018	DBLP DOI BibTeX RDF
28	Sparsh Mittal	A survey of techniques for architecting TLBs.	Concurr. Comput. Pract. Exp.	2017	DBLP DOI BibTeX RDF
28	Albert Esteve, Alberto Ros 0001, María Engracia Gómez, Antonio Robles, José Duato	TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs.	IEEE Trans. Parallel Distributed Syst.	2017	DBLP DOI BibTeX RDF
28	Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal	NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs.	NANOARCH	2015	DBLP DOI BibTeX RDF
28	Daniel Lustig, Abhishek Bhattacharjee, Margaret Martonosi	TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs.	ACM Trans. Archit. Code Optim.	2013	DBLP DOI BibTeX RDF
28	Yunfang Tai, Wanwei Cai, Qi Liu, Ge Zhang, Wenzhi Wang	Comparisons of Memory Virtualization Solutions for Architectures with Software-Managed TLBs.	NAS	2013	DBLP DOI BibTeX RDF
28	Binh Pham 0003, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee	CoLT: Coalesced Large-Reach TLBs.	MICRO	2012	DBLP DOI BibTeX RDF
28	George Theodorou, Serafeim Chatzopoulos, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos	A Software-Based Self-Test methodology for on-line testing of data TLBs.	ETS	2012	DBLP DOI BibTeX RDF
28	Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi	Shared last-level TLBs for chip multiprocessors.	HPCA	2011	DBLP DOI BibTeX RDF
28	Xiaohui Zhang, Ming Cong, Guangqiang Chen	Software and Hardware Co-designed Multi-level TLBs for Chip Multiprocessors.	CIT	2011	DBLP DOI BibTeX RDF
28	Shekhar Srikantaiah, Mahmut T. Kandemir	Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors.	MICRO	2010	DBLP DOI BibTeX RDF
28	Peter Petrov, Alex Orailoglu	Virtual Page Tag Reduction for Low-power TLBs.	ICCD	2003	DBLP DOI BibTeX RDF
28	Bruce L. Jacob, Trevor N. Mudge	Uniprocessor Virtual Memory without TLBs.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	virtual address translation, virtual caches, software-managed address translation, memory management, Virtual memory, translation lookaside buffers
28	Aamer Jaleel, Bruce L. Jacob	In-Line Interrupt Handling for Software-Managed TLBs.	ICCD	2001	DBLP DOI BibTeX RDF
28	David Channon, David Koch	Performance Analysis of Re-configurable Partitioned TLBs.	HICSS (5)	1997	DBLP DOI BibTeX RDF	Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation
28	Jang-Suk Park, Gwang Seon Ahn	A software-controlled prefetching mechanism for software-managed TLBs.	Microprocess. Microprogramming	1995	DBLP DOI BibTeX RDF
28	Patricia J. Teller, Allan Gottlieb	Locating Multiprocessor TLBs at Memory.	HICSS (1)	1994	DBLP BibTeX RDF
28	Olivier Bezie, Philip Lockwood	Beam search and partial traceback in the frame-synchronous two-level algorithm (TLBS).	ICASSP (2)	1993	DBLP DOI BibTeX RDF
28	David Nagle, Richard Uhlig, Timothy J. Stanley, Stuart Sechrest, Trevor N. Mudge, Richard B. Brown	Design Tradeoffs for Software-Managed TLBs.	ISCA	1993	DBLP DOI BibTeX RDF
17	Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt	Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power
17	Ilya Chukhman, Peter Petrov	Context-aware TLB preloading for interference reduction in embedded multi-tasked systems.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	TLB management, real-time multi-processing
17	Abhishek Bhattacharjee, Margaret Martonosi	Inter-core cooperative TLB for chip multiprocessors.	ASPLOS	2010	DBLP DOI BibTeX RDF	parallelism, prefetching, translation lookaside buffer
17	Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, Thomas Moscibroda	Dynamically replicated memory: building reliable systems from nanoscale resistive memories.	ASPLOS	2010	DBLP DOI BibTeX RDF	write endurance, phase-change memory
17	Dan Knights, Todd Mytkowicz, Peter F. Sweeney, Michael C. Mozer, Amer Diwan	Blind Optimization for Exploiting Hardware Features.	CC	2009	DBLP DOI BibTeX RDF
17	Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava	Code Transformations for TLB Power Reduction.	VLSI Design	2009	DBLP DOI BibTeX RDF
17	Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum	Impact of JVM superoperators on energy consumption in resource-constrained embedded systems.	LCTES	2008	DBLP DOI BibTeX RDF	superoperators, embedded systems, java virtual machine, energy estimation, profile-guided optimization
17	Anita Lungu, Daniel J. Sorin	Verification-Aware Microprocessor Design.	PACT	2007	DBLP DOI BibTeX RDF
17	Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell	qTLB: Looking Inside the Look-Aside Buffer.	HiPC	2007	DBLP DOI BibTeX RDF
17	Albert Meixner, Daniel J. Sorin	Unified microprocessor core storage.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	unified caching, resource allocation, microarchitecture, power-efficiency
17	Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Variation Analysis of CAM Cells.	ISQED	2007	DBLP DOI BibTeX RDF
17	Vikas Chaudhary, Lawrence T. Clark	Low-power high-performance nand match line content addressable memories.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
17	François Cantonnet, Tarek A. El-Ghazawi, Pascal Lorenz, Jaafar Gaber	Fast Address Translation Techniques for Distributed Shared Memory Compilers.	IPDPS	2005	DBLP DOI BibTeX RDF
17	Linda M. Null, Karishma Rao	CAMERA: introducing memory concepts via visualization.	SIGCSE	2005	DBLP DOI BibTeX RDF	computer memory workbenches, education, tutorial
17	Henrik Löf, Sverker Holmgren	affinity-on-next-touch: increasing the performance of an industrial PDE solver on a cc-NUMA system.	ICS	2005	DBLP DOI BibTeX RDF	TLB shoot-down, computational electro-magnetics, large pages, OpenMP, sparse matrices, conjugate gradients, cc-NUMA, page migration
17	Kostas Magoutis	Memory Management Support for Multi-Programmed Remote Direct Memory Access (RDMA) Systems.	CLUSTER	2005	DBLP DOI BibTeX RDF
17	Ismail Kadayif, Mahmut T. Kandemir, I. Demirkiran	Compiler-Guided Code Restructuring for Improving Instruction TLB Energy Behavior.	Euro-Par	2004	DBLP DOI BibTeX RDF
17	Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen	Compiler-directed code restructuring for reducing data TLB energy.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	code restructuring
17	Jack J. Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You	Accurate Cache and TLB Characterization Using Hardware Counters.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
17	Cristan Szmajda, Gernot Heiser	Variable Radix Page Table: A Page Table for Modern Architectures.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
17	Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser	Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
17	Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram	Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power TLB, multi-ported memory structures, energy optimization, low-power cache
17	Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Power efficient comparators for long arguments in superscalar processors.	ISLPED	2003	DBLP DOI BibTeX RDF	low-power comparators, superscalar datapath
17	Christopher J. Hughes, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve	RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors.	Computer	2002	DBLP DOI BibTeX RDF
17	Gokul B. Kandiraju, Anand Sivasubramaniam	Going the Distance for TLB Prefetching: An Application-Driven Study.	ISCA	2002	DBLP DOI BibTeX RDF	Application-driven Study, Simulation, Prefetching, Memory Hierarchy, Translation Lookaside Buffer
17	Zhen Fang 0002, Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee	Reevaluating Online Superpage Promotion with Hardware Support.	HPCA	2001	DBLP DOI BibTeX RDF
17	Aamer Jaleel, Bruce L. Jacob	Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers.	HiPC	2001	DBLP DOI BibTeX RDF
17	Sitaram Yadavalli, Sandip Kundu	On Fault-Simulation Through Embedded Memories On Large Industrial Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
17	Ashley Saulsbury, Fredrik Dahlgren, Per Stenström	Recency-based TLB preloading.	ISCA	2000	DBLP DOI BibTeX RDF
17	Bruce L. Jacob, Trevor N. Mudge	A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations.	ASPLOS	1998	DBLP DOI BibTeX RDF
17	Todd M. Austin, Gurindar S. Sohi	High-Bandwidth Address Translation for Multiple-Issue Processors.	ISCA	1996	DBLP DOI BibTeX RDF
17	Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad	Reducing TLB and Memory Overhead Using Online Superpage Promotion.	ISCA	1995	DBLP DOI BibTeX RDF