Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
112 | Qidong Xu, Patricia J. Teller |
Unified vs. split TLBs and caches in shared-memory MP systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 398-403, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
data references, performance evaluation, caches, discrete event simulation, shared-memory multiprocessors, shared memory systems, trace-driven simulations, cache storage, performance gains, translation-lookaside buffer |
111 | Aamer Jaleel, Bruce L. Jacob |
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(5), pp. 559-574, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Reorder-buffer (ROB), exception handlers, in-line interrupt, lock-up free, translation lookaside buffers (TLBs), performance modeling, precise interrupts |
67 | André Seznec |
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(7), pp. 924-927, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiple page size, skewed associativity, TLB |
51 | Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic |
Synonymous address compaction for energy reduction in data TLB. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 357-362, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low-power TLB, spatial and temporal locality, multi-porting |
51 | Gokul B. Kandiraju, Anand Sivasubramaniam |
Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 129-139, 2002, ACM, 1-58113-531-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | Madhusudhan Talluri, Mark D. Hill |
Surpassing the TLB Performance of Superpages with Less Operating System Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994., pp. 171-182, 1994, ACM Press, 0-89791-660-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
45 | Emre Özer 0001, Stuart Biles |
Thread Priority-Aware Random Replacement in TLBs for a High-Performance Real-Time SMT Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 376-386, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
45 | Richard Uhlig, David Nagle, Timothy J. Stanley, Trevor N. Mudge, Stuart Sechrest, Richard B. Brown |
Design Tradeoffs for Software-Managed TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Comput. Syst. ![In: ACM Trans. Comput. Syst. 12(3), pp. 175-205, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
translation lookaside buffer (TLB), trap-driven simulation, hardware monitoring |
34 | Yen-Jen Chang |
An ultra low-power TLB design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1122-1127, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Shivakumar Swaminathan, Sanjay B. Patel, James Dieffenderfer, Joel Silberman |
Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 54-58, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Magnus Ekman, Per Stenström, Fredrik Dahlgren |
TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 243-246, 2002, ACM, 1-58113-475-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
virtual caches, low-power, CMP, snoop |
34 | Adam Wiggins, Gernot Heiser |
Fast Address-Space Switching on the StrongARM SA-1100 Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACAC ![In: 5th Australasian Computer Architecture Conference (ACAC 2000), 31 January - 3 February 2000, Canberra, Australia, pp. 97-, 2000, IEEE Computer Society, 0-7695-0512-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Richard Uhlig, Trevor N. Mudge |
Trace-Driven Memory Simulation: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Comput. Surv. ![In: ACM Comput. Surv. 29(2), pp. 128-170, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
memory simulation, caches, memory management, trace-driven simulation, TLBs |
28 | Bin Gao, Qingxuan Kang, Hao-Wei Tee, Kyle Timothy Ng Chu, Alireza Sanaee, Djordje Jevdjic |
numaPTE: Managing Page-Tables and TLBs on NUMA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.15558, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
28 | Shuwen Deng, Wenjie Xiong 0001, Jakub Szefer |
Designing Secure TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 41(2), pp. 39-46, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
28 | Florian Stolz, Jan Philipp Thoma, Pascal Sasdrich, Tim Güneysu |
Risky Translations: Securing TLBs against Timing Side Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Trans. Cryptogr. Hardw. Embed. Syst. ![In: IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023(1), pp. 1-31, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | Zhenkai Zhang, Tyler N. Allen, Fan Yao, Xing Gao 0001, Rong Ge 0002 |
TunneLs for Bootlegging: Fully Reverse-Engineering GPU TLBs for Challenging Isolation Guarantees of NVIDIA MIG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCS ![In: Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, CCS 2023, Copenhagen, Denmark, November 26-30, 2023, pp. 960-974, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
28 | Florian Stolz, Jan Philipp Thoma, Pascal Sasdrich, Tim Güneysu |
Risky Translations: Securing TLBs against Timing Side Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2022, pp. 1394, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP BibTeX RDF |
|
28 | Chao Yu 0001, Yuebin Bai, Rui Wang 0014 |
Enabling Large-Reach TLBs for High-Throughput Processors by Exploiting Memory Subregion Contiguity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2110.08613, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
28 | Chandrashis Mazumdar, Prachatos Mitra, Arkaprava Basu |
Dead Page and Dead Block Predictors: Cleaning TLBs and Caches Together. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: IEEE International Symposium on High-Performance Computer Architecture, HPCA 2021, Seoul, South Korea, February 27 - March 3, 2021, pp. 507-519, 2021, IEEE, 978-1-6654-2235-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
28 | Steffen Maass, Mohan Kumar Kumar, Taesoo Kim, Tushar Krishna, Abhishek Bhattacharjee |
ECOTLB: Eventually Consistent TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 17(4), pp. 27:1-27:24, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
28 | Jakob Koschel, Cristiano Giuffrida, Herbert Bos, Kaveh Razavi |
TagBleed: Breaking KASLR on the Isolated Kernel Address Space using Tagged TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroS&P ![In: IEEE European Symposium on Security and Privacy, EuroS&P 2020, Genoa, Italy, September 7-11, 2020, pp. 309-321, 2020, IEEE, 978-1-7281-5087-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
28 | Hussein Elnawawy, Rangeen Basu Roy Chowdhury, Amro Awad, Gregory T. Byrd |
Diligent TLBs: a mechanism for exploiting heterogeneity in TLB miss behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the ACM International Conference on Supercomputing, ICS 2019, Phoenix, AZ, USA, June 26-28, 2019, pp. 195-205, 2019, ACM, 978-1-4503-6079-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Zi Yan, Daniel Lustig, David W. Nellans, Abhishek Bhattacharjee |
Translation ranger: operating system support for contiguity-aware TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 46th International Symposium on Computer Architecture, ISCA 2019, Phoenix, AZ, USA, June 22-26, 2019, pp. 698-710, 2019, ACM, 978-1-4503-6669-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Shuwen Deng, Wenjie Xiong 0001, Jakub Szefer |
Secure TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 46th International Symposium on Computer Architecture, ISCA 2019, Phoenix, AZ, USA, June 22-26, 2019, pp. 346-359, 2019, ACM, 978-1-4503-6669-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
28 | Srikant Bharadwaj, Guilherme Cox, Tushar Krishna, Abhishek Bhattacharjee |
Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018, pp. 271-284, 2018, IEEE Computer Society, 978-1-5386-6240-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
28 | Sparsh Mittal |
A survey of techniques for architecting TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Concurr. Comput. Pract. Exp. ![In: Concurr. Comput. Pract. Exp. 29(10), 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Albert Esteve, Alberto Ros 0001, María Engracia Gómez, Antonio Robles, José Duato |
TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 28(8), pp. 2401-2413, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
28 | Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal |
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 51-56, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
28 | Daniel Lustig, Abhishek Bhattacharjee, Margaret Martonosi |
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 10(1), pp. 2:1-2:38, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Yunfang Tai, Wanwei Cai, Qi Liu, Ge Zhang, Wenzhi Wang |
Comparisons of Memory Virtualization Solutions for Architectures with Software-Managed TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NAS ![In: IEEE Eighth International Conference on Networking, Architecture and Storage, NAS 2013, Xi'an, Shaanxi, China, July 17-19, 2013, pp. 125-130, 2013, IEEE Computer Society, 978-0-7695-5034-3. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
28 | Binh Pham 0003, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee |
CoLT: Coalesced Large-Reach TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2012, Vancouver, BC, Canada, December 1-5, 2012, pp. 258-269, 2012, IEEE Computer Society, 978-1-4673-4819-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | George Theodorou, Serafeim Chatzopoulos, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos |
A Software-Based Self-Test methodology for on-line testing of data TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012, pp. 1, 2012, IEEE Computer Society, 978-1-4673-0697-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
28 | Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi |
Shared last-level TLBs for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 62-63, 2011, IEEE Computer Society, 978-1-4244-9432-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Xiaohui Zhang, Ming Cong, Guangqiang Chen |
Software and Hardware Co-designed Multi-level TLBs for Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 11th IEEE International Conference on Computer and Information Technology, CIT 2011, Pafos, Cyprus, 31 August-2 September 2011, pp. 609-614, 2011, IEEE Computer Society, 978-0-7695-4388-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
28 | Shekhar Srikantaiah, Mahmut T. Kandemir |
Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA, pp. 313-324, 2010, IEEE Computer Society, 978-0-7695-4299-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
28 | Peter Petrov, Alex Orailoglu |
Virtual Page Tag Reduction for Low-power TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 371-374, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Bruce L. Jacob, Trevor N. Mudge |
Uniprocessor Virtual Memory without TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(5), pp. 482-499, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
virtual address translation, virtual caches, software-managed address translation, memory management, Virtual memory, translation lookaside buffers |
28 | Aamer Jaleel, Bruce L. Jacob |
In-Line Interrupt Handling for Software-Managed TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 62-67, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | David Channon, David Koch |
Performance Analysis of Re-configurable Partitioned TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (5) ![In: 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA, pp. 168-177, 1997, IEEE Computer Society, 0-8186-7734-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation |
28 | Jang-Suk Park, Gwang Seon Ahn |
A software-controlled prefetching mechanism for software-managed TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microprogramming ![In: Microprocess. Microprogramming 41(2), pp. 121-136, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Patricia J. Teller, Allan Gottlieb |
Locating Multiprocessor TLBs at Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 27th Annual Hawaii International Conference on System Sciences (HICSS-27), January 4-7, 1994, Maui, Hawaii, USA, pp. 554-563, 1994, IEEE Computer Society, 0-8186-5090-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP BibTeX RDF |
|
28 | Olivier Bezie, Philip Lockwood |
Beam search and partial traceback in the frame-synchronous two-level algorithm (TLBS). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP (2) ![In: IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '93, Minneapolis, Minnesota, USA, April 27-30, 1993, pp. 511-514, 1993, IEEE Computer Society, 0-7803-7402-9. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
28 | David Nagle, Richard Uhlig, Timothy J. Stanley, Stuart Sechrest, Trevor N. Mudge, Richard B. Brown |
Design Tradeoffs for Software-Managed TLBs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, USA, May 1993, pp. 27-38, 1993, ACM, 0-8186-3810-9. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil D. Dutt |
Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 297-308, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multiple sleep mode, peripheral circuits, sram memory, temperature reduction, leakage power |
17 | Ilya Chukhman, Peter Petrov |
Context-aware TLB preloading for interference reduction in embedded multi-tasked systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 401-404, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
TLB management, real-time multi-processing |
17 | Abhishek Bhattacharjee, Margaret Martonosi |
Inter-core cooperative TLB for chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 359-370, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parallelism, prefetching, translation lookaside buffer |
17 | Engin Ipek, Jeremy Condit, Edmund B. Nightingale, Doug Burger, Thomas Moscibroda |
Dynamically replicated memory: building reliable systems from nanoscale resistive memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010, pp. 3-14, 2010, ACM, 978-1-60558-839-1. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
write endurance, phase-change memory |
17 | Dan Knights, Todd Mytkowicz, Peter F. Sweeney, Michael C. Mozer, Amer Diwan |
Blind Optimization for Exploiting Hardware Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 18th International Conference, CC 2009, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009, York, UK, March 22-29, 2009. Proceedings, pp. 251-265, 2009, Springer, 978-3-642-00721-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivastava |
Code Transformations for TLB Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 413-418, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Carmen Badea, Alexandru Nicolau, Alexander V. Veidenbaum |
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, AZ, USA, June 12-13, 2008, pp. 23-30, 2008, ACM, 978-1-60558-104-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
superoperators, embedded systems, java virtual machine, energy estimation, profile-guided optimization |
17 | Anita Lungu, Daniel J. Sorin |
Verification-Aware Microprocessor Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 83-93, 2007, IEEE Computer Society, 0-7695-2944-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Omesh Tickoo, Hari Kannan, Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer 0001, Donald Newell |
qTLB: Looking Inside the Look-Aside Buffer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2007, 14th International Conference, Goa, India, December 18-21, 2007, Proceedings, pp. 107-118, 2007, Springer, 978-3-540-77219-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Albert Meixner, Daniel J. Sorin |
Unified microprocessor core storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 23-34, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
unified caching, resource allocation, microarchitecture, power-efficiency |
17 | Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin |
Variation Analysis of CAM Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 333-338, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Vikas Chaudhary, Lawrence T. Clark |
Low-power high-performance nand match line content addressable memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 895-905, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | François Cantonnet, Tarek A. El-Ghazawi, Pascal Lorenz, Jaafar Gaber |
Fast Address Translation Techniques for Distributed Shared Memory Compilers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Linda M. Null, Karishma Rao |
CAMERA: introducing memory concepts via visualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGCSE ![In: Proceedings of the 36th SIGCSE Technical Symposium on Computer Science Education, SIGCSE 2005, St. Louis, Missouri, USA, February 23-27, 2005, pp. 96-100, 2005, ACM, 1-58113-997-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
computer memory workbenches, education, tutorial |
17 | Henrik Löf, Sverker Holmgren |
affinity-on-next-touch: increasing the performance of an industrial PDE solver on a cc-NUMA system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, Massachusetts, USA, June 20-22, 2005, pp. 387-392, 2005, ACM, 1-59593-167-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
TLB shoot-down, computational electro-magnetics, large pages, OpenMP, sparse matrices, conjugate gradients, cc-NUMA, page migration |
17 | Kostas Magoutis |
Memory Management Support for Multi-Programmed Remote Direct Memory Access (RDMA) Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2005 IEEE International Conference on Cluster Computing (CLUSTER 2005), September 26 - 30, 2005, Boston, Massachusetts, USA, pp. 1-8, 2005, IEEE Computer Society, 0-7803-9485-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Ismail Kadayif, Mahmut T. Kandemir, I. Demirkiran |
Compiler-Guided Code Restructuring for Improving Instruction TLB Energy Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2004 Parallel Processing, 10th International Euro-Par Conference, Pisa, Italy, August 31-September 3, 2004, Proceedings, pp. 304-309, 2004, Springer, 3-540-22924-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen |
Compiler-directed code restructuring for reducing data TLB energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 98-103, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
code restructuring |
17 | Jack J. Dongarra, Shirley Moore, Philip Mucci, Keith Seymour, Haihang You |
Accurate Cache and TLB Characterization Using Hardware Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III, pp. 432-439, 2004, Springer, 3-540-22116-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Cristan Szmajda, Gernot Heiser |
Variable Radix Page Table: A Page Table for Modern Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 290-304, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Adam Wiggins, Harvey Tuch, Volkmar Uhlig, Gernot Heiser |
Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 8th Asia-Pacific Conference, ACSAC 2003, Aizu-Wakamatsu, Japan, September 23-26, 2003, Proceedings, pp. 352-364, 2003, Springer, 3-540-20122-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Hsien-Hsin S. Lee, Chinnakrishnan S. Ballapuram |
Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 306-311, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low-power TLB, multi-ported memory structures, energy optimization, low-power cache |
17 | Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Power efficient comparators for long arguments in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 378-383, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low-power comparators, superscalar datapath |
17 | Christopher J. Hughes, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve |
RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 35(2), pp. 40-49, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
17 | Gokul B. Kandiraju, Anand Sivasubramaniam |
Going the Distance for TLB Prefetching: An Application-Driven Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 195-206, 2002, IEEE Computer Society, 0-7695-1605-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Application-driven Study, Simulation, Prefetching, Memory Hierarchy, Translation Lookaside Buffer |
17 | Zhen Fang 0002, Lixin Zhang 0002, John B. Carter, Wilson C. Hsieh, Sally A. McKee |
Reevaluating Online Superpage Promotion with Hardware Support. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 63-72, 2001, IEEE Computer Society, 0-7695-1019-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Aamer Jaleel, Bruce L. Jacob |
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2001, 8th International Conference, Hyderabad, India, December, 17-20, 2001, Proceedings, pp. 282-293, 2001, Springer, 3-540-43009-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Sitaram Yadavalli, Sandip Kundu |
On Fault-Simulation Through Embedded Memories On Large Industrial Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 117-121, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Ashley Saulsbury, Fredrik Dahlgren, Per Stenström |
Recency-based TLB preloading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 117-127, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Bruce L. Jacob, Trevor N. Mudge |
A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998., pp. 295-306, 1998, ACM Press, 1-58113-107-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Todd M. Austin, Gurindar S. Sohi |
High-Bandwidth Address Translation for Multiple-Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 158-167, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad |
Reducing TLB and Memory Overhead Using Online Superpage Promotion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 176-187, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|