Search results for "TLM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
114	Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil	TLM: Crossing Over From Buzz To Adoption.	DAC	2007	DBLP DOI BibTeX RDF
108	Tayeb Bouhadiba, Florence Maraninchi, Giovanni Funchal	Formal and executable contracts for transaction-level modeling in SystemC.	EMSOFT	2009	DBLP DOI BibTeX RDF	formal component models, systems-on-a-chip, virtual prototyping, transaction-level-modeling
104	Gunar Schirner, Rainer Dömer	Accurate yet fast modeling of real-time communication.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	result oriented modeling, system level design, real-time communication, CAN, controller area network, transaction level model, TLM, ROM
100	Olivier Ponsini, Wendelin Serwe	A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS.	FM	2008	DBLP DOI BibTeX RDF
100	Lochi Yu, Samar Abdi	Automatic SystemC TLM generation for custom communication platforms.	ICCD	2007	DBLP DOI BibTeX RDF
94	Gunar Schirner, Rainer Dömer	Quantitative analysis of the speed/accuracy trade-off in transaction level modeling.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	system-on-chip, System level design, transaction level modeling
90	Adam Donlin	Transaction level modeling: flows and use models.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	design abstractions, use models, design flows, TLM
87	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva 0001	Towards Equivalence Checking Between TLM and RTL Models.	MEMOCODE	2007	DBLP DOI BibTeX RDF
74	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL.	DATE	2006	DBLP DOI BibTeX RDF
74	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington	Exploiting TLM and object introspection for system-level simulation.	DATE	2006	DBLP DOI BibTeX RDF
67	Gunar Schirner, Rainer Dömer	Fast and accurate transaction level models using result oriented modeling.	ICCAD	2006	DBLP DOI BibTeX RDF
60	Laurence Pierre, Luca Ferro	A Tractable and Fast Method for Monitoring SystemC TLM Specifications.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
60	Claude Helmstetter, Olivier Ponsini	A Comparison of Two SystemC/TLM Semantics for Formal Verification.	MEMOCODE	2008	DBLP DOI BibTeX RDF
60	Nicola Bombieri, Nicola Deganello, Franco Fummi	Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation.	DATE	2008	DBLP DOI BibTeX RDF
60	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	A Mutation Model for the SystemC TLM 2.0 Communication Interfaces.	DATE	2008	DBLP DOI BibTeX RDF
60	Gunar Schirner, Rainer Dömer	Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
60	Bernhard Niemann, Christian Haubelt	Towards a Unified Execution Model for Transactions in TLM.	MEMOCODE	2007	DBLP DOI BibTeX RDF
60	Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax	Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates.	VLSI Design	2001	DBLP DOI BibTeX RDF
56	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	TBV, Model checking, fault models, functional verification, TLM
56	Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Andrea Fedeli	Hybrid, Incremental Assertion-Based Verification for TLM Design Flows.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	hybrid, RTL, design flow, TLM, assertion-based verification
54	Frederic Doucet, R. K. Shyamasundar, Ingolf H. Krüger, Saurabh Joshi 0001, Rajesh K. Gupta 0001	Reactivity in SystemC Transaction-Level Models.	Haifa Verification Conference	2007	DBLP DOI BibTeX RDF
50	Wolfgang Klingauf, Robert Günzel, Christian Schröder	Embedded software development on top of transaction-level models.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	hardware-software communication, middleware, SoC, embedded software, SystemC, HPC, TLM
47	Eric Cheung, Harry Hsieh, Felice Balarin	Memory subsystem simulation in software TLM/T models.	ASP-DAC	2009	DBLP DOI BibTeX RDF
47	Ka Lok Man, Michele Mercaldi, H. L. Leung, J. Huang	Performance and Functional Analysis of TLM Models in the SHE Methodology.	CSSE (4)	2008	DBLP DOI BibTeX RDF
47	Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed	Efficient assertion based verification using TLM.	DATE	2006	DBLP DOI BibTeX RDF
47	Emmanuel Viaud, François Pêcheux, Alain Greiner	An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles.	DATE	2006	DBLP DOI BibTeX RDF
47	Ayhan Akbal, Hasan H. Balik	Fast Rigorous Analysis of Rectangular Waveguides by Optimized 2D-TLM.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
47	Liang Zhu, Jinian Bian	From Software to Hardware - A Novel TLM Auto-Generating Method.	APCCAS	2006	DBLP DOI BibTeX RDF
47	Baohua Wang, Pinaki Mazumder	Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit models.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
47	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
47	Baohua Wang, Pinaki Mazumder	Subgridding method for speeding up FD-TLM circuit simulation.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
43	Ke Yu, Neil C. Audsley	Combining Behavioural Real-time Software Modelling with the OSCI TLM-2.0 Communication Standard.	CIT	2010	DBLP DOI BibTeX RDF	Simulation, Software, SystemC, TLM
43	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel	Retargetable generation of TLM bus interfaces for MP-SoC platforms.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC
42	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction.	ETS	2011	DBLP DOI BibTeX RDF	RTL fault simulation, fault simulation acceleration, RTL-to-TLM abstraction
40	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based communication architectures at the CCATB abstraction.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus
40	Adnane Latif, Rachid Hilal, Abdellah Ait Ouahman	Investigation on folded patch antenna for cellular applications.	ISCC	2008	DBLP DOI BibTeX RDF
40	Alisson Vasconcelos de Brito, Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001, Elmar U. K. Melcher	Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC.	ISVLSI	2007	DBLP DOI BibTeX RDF
40	Ping Jack Soh, Abdullah Al-Hadi Azremi, Rosemizi Abd Rahim, H. Dayang, M. T. Jusoh	Simplified Modeling, Simulation and Performance Analysis Using Circuit Model for a Corporate Feed Microstrip Patch Array.	Asia International Conference on Modelling and Simulation	2007	DBLP DOI BibTeX RDF	microship antennas, Moment Methods, Transmission-Line-Matrix methods, circuit simulation, Antenna array
40	Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu	Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.	ISCAS	2007	DBLP DOI BibTeX RDF
40	Gunar Schirner, Rainer Dömer	Quantitative analysis of transaction level models for the AMBA bus.	DATE	2006	DBLP DOI BibTeX RDF
40	Alena Tsikhanovich, Frédéric Rousseau 0001, El Mostapha Aboulhamid, Guy Bois	Transaction Level Modeling in Hardware/Software System Design using .Net Framework.	CCECE	2006	DBLP DOI BibTeX RDF
40	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Extending the transaction level modeling approach for fast communication architecture exploration.	DAC	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
40	Yu-Min Lee, Charlie Chung-Ping Chen	The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method .	DATE	2003	DBLP DOI BibTeX RDF
39	Antonio Genov	Power estimation framework based on SystemC-TLM performance models of SoC interconnect and memory systems. (Estimation de la consommation basée sur les modèles de performance SystemC-TLM des systèmes d'interconnexion et de mémoire des SoC).		2021	RDF
39	Denis Becker	Parallel System C/TLM Simulation of Hardware Components described for High-Level Synthesis. (Simulation Parallèle en SystemC/TLM de Composants Matériels décrits pour la Synthèse de Haut-Niveau).		2017	RDF
39	Claude Helmstetter	TLM.open: a SystemC/TLM Frontend for the CADP Verification Toolbox.	Leibniz Trans. Embed. Syst.	2014	DBLP DOI BibTeX RDF
39	Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Sara Vinco	Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis.	MTV	2012	DBLP DOI BibTeX RDF
39	David J. Greaves, Muhammad Mehboob Yasin	TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0.	FDL (Selected Papers)	2012	DBLP DOI BibTeX RDF
39	David J. Greaves, Muhammad Mehboob Yasin	TLM POWER3: Power estimation methodology for SystemC TLM 2.0.	FDL	2012	DBLP BibTeX RDF
39	Nicola Bombieri, Franco Fummi, Valerio Guarnieri	Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
39	Dzianis Lukashevich	Model Order Reduction (MOR) in Transmission Line Matrix (TLM) Method (Anwendung der Modell-Ordnungsreduktion (MOR) auf die Transmission Line Matrix (TLM)-Methode) (PDF / PS)		2007	RDF
37	Vicente Galiano Ibarra, Marcos Martínez, Héctor Migallón Gomis, David Pérez-Caparrós, Carlos Quesada	A Case Study in Distributing a SystemC Model.	IWANN (2)	2009	DBLP DOI BibTeX RDF	Distributed Systems, MPI, SystemC, PLC, Serialization, TLM, PDES
37	Grant Martin	The First Transaction, but not the Last.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	SystemC, transaction-level modeling, ESL, TLM
33	Huseyin Dogan, Michael Henshaw, Esmond Neil Urwin	A 'Soft' Approach to TLM Requirements Capture to Support Through-Life Management.	KSEM	2009	DBLP DOI BibTeX RDF	Through-Life Management, Soft Systems, Knowledge Management, Requirements Analysis, Interactive Management
33	Christian Schröder, Wolfgang Klingauf, Robert Günzel, Mark Burton, Eric Roesler	Configuration and control of SystemC models using TLM middleware.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	OSCI CCI, greenconfig, greencontrol, control, analysis, configuration, inspection, systemc
33	Sudipta Kundu, Malay K. Ganai, Rajesh Gupta 0001	Partial order reduction for scalable testing of systemC TLM designs.	DAC	2008	DBLP DOI BibTeX RDF	simulation, verification, testing, partial-order reduction
33	Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi	Functional Test-Case Generation by a Control Transaction Graph for TLM Verification.	DSD	2007	DBLP DOI BibTeX RDF
33	Wolfgang Ecker, Volkan Esen, Michael Hull	Execution semantics and formalisms for multi-abstraction TLM assertions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
33	Wolfgang Klingauf, Hagen Gädke, Robert Günzel	TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
33	Nicola Bombieri, Franco Fummi, Davide Quaglia	TLM/network design space exploration for networked embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	transaction-level modeling, networked embedded systems
27	Yacine Amara, Xavier Marsault	A GPU Tile-Load-Map architecture for terrain rendering: theory and applications.	Vis. Comput.	2009	DBLP DOI BibTeX RDF	GPU architecture, Data amplification, Seed model, Level of detail, Terrain rendering
27	Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski	Hardware-dependent software synthesis for many-core embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
27	Luciano Ost, Guilherme Montez Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp da Rosa, Fernando Moraes 0001	A high abstraction, high accuracy power estimation model for networks-on-chip.	SBCCI	2009	DBLP DOI BibTeX RDF	high abstraction modeling, networks-on-chip, power modeling
27	David W. Bauer, Christopher D. Carothers, Akintayo Holder	Scalable Time Warp on Blue Gene Supercomputers.	PADS	2009	DBLP DOI BibTeX RDF	Blue Gene Supercomputer, Time Warp
27	Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu	SoC-level risk assessment using FMEA approach in system design with SystemC.	SIES	2009	DBLP DOI BibTeX RDF
27	Sandro Penolazzi, Ahmed Hemani, Luca Bolognino	A General Approach to High-Level Energy and Performance Estimation in SoCs.	VLSI Design	2009	DBLP DOI BibTeX RDF
27	Giovanni Agosta, Francesco Bruschi, Donatella Sciuto	Static Analysis of Transaction-Level Communication Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
27	Yonghyun Hwang, Samar Abdi, Daniel Gajski	Cycle-approximate Retargetable Performance Estimation at the Transaction Level.	DATE	2008	DBLP DOI BibTeX RDF
27	Alessandro Mignogna, Massimo Conti, M. D'Angelo, Massimo Baleani, Alberto Ferrari	Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard.	DSD	2008	DBLP DOI BibTeX RDF
27	Girish Venkataramani, Seth Copen Goldstein	Slack analysis in the system design loop.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	slack analysis, system design loop, timing update
27	Daniel D. Gajski, Samar Abdi, Ines Viskic	Model Based Synthesis of Embedded Software.	SEUS	2008	DBLP DOI BibTeX RDF
27	Giovanni Beltrame, Donatella Sciuto, Cristina Silvano	Multi-Accuracy Power and Performance Transaction-Level Modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
27	Ines Viskic, Samar Abdi, Daniel D. Gajski	Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.	LCTES	2007	DBLP DOI BibTeX RDF	custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication
27	Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull	Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance.	DATE	2007	DBLP DOI BibTeX RDF
27	Grégory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier	Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM.	DATE	2007	DBLP DOI BibTeX RDF
27	Bruno C. Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araújo, Edna Barros, Willians Azevedo	A computational reflection mechanism to support platform debugging in SystemC.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	debugging, system architecture, platform-based design, computational reflection
27	Nicola Bombieri, Franco Fummi, Graziano Pravadelli	A methodology for abstracting RTL designs into TL descriptions.	MEMOCODE	2006	DBLP DOI BibTeX RDF
27	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
27	Nicola Bombieri, Andrea Fedeli, Franco Fummi	On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling.	MTV	2005	DBLP DOI BibTeX RDF
27	Wolfgang Klingauf	Systematic Transaction Level Modeling of Embedded Systems with SystemC.	DATE	2005	DBLP DOI BibTeX RDF
27	Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo	Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture.	DATE	2005	DBLP DOI BibTeX RDF
27	Jin Lee, Sin-Chong Park	Transaction level modeling of IEEE 802.11 system.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
27	Yu-Min Lee, Charlie Chung-Ping Chen	The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
27	Rohit Jindal, Kshitiz Jain	Verification of Transaction-Level SystemC models using RTL Testbenches.	MEMOCODE	2003	DBLP DOI BibTeX RDF
27	Heinz-Josef Schlebusch, Gary Smith 0001, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel	Transaction Based Design: Another Buzzword or the Solution to a Design Problem?	DATE	2003	DBLP DOI BibTeX RDF
27	Haobo Yu, Andreas Gerstlauer, Daniel Gajski	RTOS scheduling in transaction level models.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	SpecC, model, system design, RTOS
23	P. Ezudheen, Priya Chandran, Joy Chandra, Biju Puthur Simon, Deepak Ravi	Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines.	PADS	2009	DBLP DOI BibTeX RDF	OSCI, Core affinity, SoC, SystemC, SMP, TLM
23	Giovanni Beltrame, Cristiana Bolchini, Antonio Miele	Multi-level fault modeling for transaction-level specifications.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault modeling, soft error, system-level design, tlm
23	Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado	An open-source binary utility generator.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Platform debugging, retargetable tools, TLM
23	Thomas Lenart, Henrik Svensson, Viktor Öwall	A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing.	DELTA	2008	DBLP DOI BibTeX RDF	SCENIC, Network-on-Chip, Reconfigurable Computing, TLM, 2D Mesh
23	Armando Sánchez-Peña, Pedro P. Carballo, Luz García 0001, Antonio Núñez	VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems.	DSD	2006	DBLP DOI BibTeX RDF	AMBA 3 AXI, VIPACES, Virtual Components, Verification, Test, System-on-Chip (SoC), IP, DCT, Emulation, SystemC, Environment, TLM, IDCT, VIP
23	Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard	Maintaining consistency between systemC and RTL system designs.	DAC	2006	DBLP DOI BibTeX RDF	SPIRIT, transactor, verification, systemC, RTL, TLM, testbench, VIP
23	Stuart Swan	SystemC transaction level models and RTL verification.	DAC	2006	DBLP DOI BibTeX RDF	RTL verification, hardware/software co-verification, systemC, hardware/software co-design, transaction level model, TLM
23	Wolfgang Klingauf, Robert Günzel, Oliver Bringmann 0001, Pavel Parfuntseu, Mark Burton	GreenBus: a generic interconnect fabric for transaction level modelling.	DAC	2006	DBLP DOI BibTeX RDF	SoC, SystemC, TLM, on-chip communication
23	Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.	ASP-DAC	2005	DBLP DOI BibTeX RDF	SoC, systemc, transaction-level modeling, TLM, simulation acceleration
22	Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl	System prototypes: virtual, hardware or hybrid?	DAC	2009	DBLP DOI BibTeX RDF	SystemC TLM, hardware/software co-verification, rapid prototype, embedded software, virtual prototype, virtual platform, system validation, FPGA prototype, system prototype
22	D. V. Das	EM simulation [ICs and MCMs].	VLSI Design	1995	DBLP DOI BibTeX RDF	electromagnetic field theory, transmission line matrix methods, integrated circuit packaging, EM simulation, emitted radiation, transmission line matrix method, electromagnetic simulation, TLM method, signal integrity, multichip modules, IC, MCM, electromagnetic field
20	Alfonso Salinas, Jorge Porti, Enrique A. Navarro, Sergio Toledo-Redondo, Inmaculada Albert, Aida Castilla, Víctor Montagud-Camps	A 3D TLM code for the study of the ELF electromagnetic wave propagation in the Earth's atmosphere.	Comput. Geosci.	2024	DBLP DOI BibTeX RDF
20	Yangjun Wu, Kebin Fang, Dongxiang Zhang, Han Wang, Hao Zhang, Gang Chen 0001	TLM: Token-Level Masking for Transformers.	CoRR	2023	DBLP DOI BibTeX RDF
20	Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Lukas Jünger 0001, Jan Henrik Weinstock, Rainer Leupers	Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms.	CODES+ISSS	2023	DBLP BibTeX RDF