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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 193 occurrences of 110 keywords
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Results
Found 339 publication records. Showing 339 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
114 | Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil |
TLM: Crossing Over From Buzz To Adoption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 444-445, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
108 | Tayeb Bouhadiba, Florence Maraninchi, Giovanni Funchal |
Formal and executable contracts for transaction-level modeling in SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Proceedings of the 9th ACM & IEEE International conference on Embedded software, EMSOFT 2009, Grenoble, France, October 12-16, 2009, pp. 97-106, 2009, ACM, 978-1-60558-627-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
formal component models, systems-on-a-chip, virtual prototyping, transaction-level-modeling |
104 | Gunar Schirner, Rainer Dömer |
Accurate yet fast modeling of real-time communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 70-75, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
result oriented modeling, system level design, real-time communication, CAN, controller area network, transaction level model, TLM, ROM |
100 | Olivier Ponsini, Wendelin Serwe |
A Schedulerless Semantics of TLM Models Written in SystemC Via Translation into LOTOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FM ![In: FM 2008: Formal Methods, 15th International Symposium on Formal Methods, Turku, Finland, May 26-30, 2008, Proceedings, pp. 278-293, 2008, Springer, 978-3-540-68235-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
100 | Lochi Yu, Samar Abdi |
Automatic SystemC TLM generation for custom communication platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 41-46, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
94 | Gunar Schirner, Rainer Dömer |
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(1), pp. 4:1-4:29, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
system-on-chip, System level design, transaction level modeling |
90 | Adam Donlin |
Transaction level modeling: flows and use models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004, pp. 75-80, 2004, ACM, 1-58113-937-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design abstractions, use models, design flows, TLM |
87 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, João Marques-Silva 0001 |
Towards Equivalence Checking Between TLM and RTL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30 - June 1st, Nice, France, pp. 113-122, 2007, IEEE Computer Society, 1-4244-1050-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
74 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1007-1012, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
74 | Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Damien Lyonnard, Chuck Pilkington |
Exploiting TLM and object introspection for system-level simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 100-105, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Gunar Schirner, Rainer Dömer |
Fast and accurate transaction level models using result oriented modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 363-368, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
60 | Laurence Pierre, Luca Ferro |
A Tractable and Fast Method for Monitoring SystemC TLM Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(10), pp. 1346-1356, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Claude Helmstetter, Olivier Ponsini |
A Comparison of Two SystemC/TLM Semantics for Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), June 5-7, 2008, Anaheim, CA, USA, pp. 59-68, 2008, IEEE Computer Society, 978-1-4244-2417-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Nicola Bombieri, Nicola Deganello, Franco Fummi |
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 15-20, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 396-401, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Gunar Schirner, Rainer Dömer |
Result-Oriented Modeling - A Novel Technique for Fast and Accurate TLM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9), pp. 1688-1699, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Bernhard Niemann, Christian Haubelt |
Towards a Unified Execution Model for Transactions in TLM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30 - June 1st, Nice, France, pp. 103-112, 2007, IEEE Computer Society, 1-4244-1050-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
60 | Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax |
Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 470-474, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
56 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(3), pp. 47:1-47:22, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
TBV, Model checking, fault models, functional verification, TLM |
56 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Andrea Fedeli |
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 140-152, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hybrid, RTL, design flow, TLM, assertion-based verification |
54 | Frederic Doucet, R. K. Shyamasundar, Ingolf H. Krüger, Saurabh Joshi 0001, Rajesh K. Gupta 0001 |
Reactivity in SystemC Transaction-Level Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Haifa Verification Conference ![In: Hardware and Software: Verification and Testing, Third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007, Proceedings, pp. 34-50, 2007, Springer, 978-3-540-77964-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Wolfgang Klingauf, Robert Günzel, Christian Schröder |
Embedded software development on top of transaction-level models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 27-32, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
hardware-software communication, middleware, SoC, embedded software, SystemC, HPC, TLM |
47 | Eric Cheung, Harry Hsieh, Felice Balarin |
Memory subsystem simulation in software TLM/T models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 811-816, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Ka Lok Man, Michele Mercaldi, H. L. Leung, J. Huang |
Performance and Functional Analysis of TLM Models in the SHE Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (4) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 4: Embedded Programming / Database Technology / Neural Networks and Applications / Other Applications, December 12-14, 2008, Wuhan, China, pp. 37-40, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
47 | Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed |
Efficient assertion based verification using TLM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 106-111, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Emmanuel Viaud, François Pêcheux, Alain Greiner |
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 94-99, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Ayhan Akbal, Hasan H. Balik |
Fast Rigorous Analysis of Rectangular Waveguides by Optimized 2D-TLM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (4) ![In: Computational Science - ICCS 2006, 6th International Conference, Reading, UK, May 28-31, 2006, Proceedings, Part IV, pp. 631-637, 2006, Springer, 3-540-34385-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Liang Zhu, Jinian Bian |
From Software to Hardware - A Novel TLM Auto-Generating Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1725-1728, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
47 | Baohua Wang, Pinaki Mazumder |
Integrating lumped networks into full wave TLM/FDTD methods using passive discrete circuit models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1948-1951, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Sudeep Pasricha, Mohamed Ben-Romdhane |
Using TLM for Exploring Bus-based SoC Communication Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 79-85, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Baohua Wang, Pinaki Mazumder |
Subgridding method for speeding up FD-TLM circuit simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 20-23, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
43 | Ke Yu, Neil C. Audsley |
Combining Behavioural Real-time Software Modelling with the OSCI TLM-2.0 Communication Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 1825-1832, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Simulation, Software, SystemC, TLM |
43 | Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel |
Retargetable generation of TLM bus interfaces for MP-SoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2005, Jersey City, NJ, USA, September 19-21, 2005, pp. 249-254, 2005, ACM, 1-59593-161-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC |
42 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, pp. 117-122, 2011, IEEE Computer Society, 978-0-7695-4433-5. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
RTL fault simulation, fault simulation acceleration, RTL-to-TLM abstraction |
40 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane |
Fast exploration of bus-based communication architectures at the CCATB abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(2), pp. 22:1-22:32, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus |
40 | Adnane Latif, Rachid Hilal, Abdellah Ait Ouahman |
Investigation on folded patch antenna for cellular applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the 13th IEEE Symposium on Computers and Communications (ISCC 2008), July 6-9, Marrakech, Morocco, pp. 824-830, 2008, IEEE Computer Society, 978-1-4244-2702-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
40 | Alisson Vasconcelos de Brito, Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001, Elmar U. K. Melcher |
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil, pp. 35-40, 2007, IEEE Computer Society, 0-7695-2896-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Ping Jack Soh, Abdullah Al-Hadi Azremi, Rosemizi Abd Rahim, H. Dayang, M. T. Jusoh |
Simplified Modeling, Simulation and Performance Analysis Using Circuit Model for a Corporate Feed Microstrip Patch Array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia International Conference on Modelling and Simulation ![In: First Asia International Conference on Modelling and Simulation, AMS 2007, Phuket, Thailand, March 27-30, 2007, pp. 253-257, 2007, IEEE Computer Society, 978-0-7695-2845-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
microship antennas, Moment Methods, Transmission-Line-Matrix methods, circuit simulation, Antenna array |
40 | Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu |
Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 409-412, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
40 | Gunar Schirner, Rainer Dömer |
Quantitative analysis of transaction level models for the AMBA bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 230-235, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Alena Tsikhanovich, Frédéric Rousseau 0001, El Mostapha Aboulhamid, Guy Bois |
Transaction Level Modeling in Hardware/Software System Design using .Net Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 140-143, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
40 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane |
Extending the transaction level modeling approach for fast communication architecture exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 113-118, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA |
40 | Yu-Min Lee, Charlie Chung-Ping Chen |
The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 11020-11025, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
39 | Antonio Genov |
Power estimation framework based on SystemC-TLM performance models of SoC interconnect and memory systems. (Estimation de la consommation basée sur les modèles de performance SystemC-TLM des systèmes d'interconnexion et de mémoire des SoC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2021 |
RDF |
|
39 | Denis Becker |
Parallel System C/TLM Simulation of Hardware Components described for High-Level Synthesis. (Simulation Parallèle en SystemC/TLM de Composants Matériels décrits pour la Synthèse de Haut-Niveau). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2017 |
RDF |
|
39 | Claude Helmstetter |
TLM.open: a SystemC/TLM Frontend for the CADP Verification Toolbox. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Leibniz Trans. Embed. Syst. ![In: Leibniz Trans. Embed. Syst. 1(1), pp. 02:1-02:18, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
39 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli, Sara Vinco |
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: 13th International Workshop on Microprocessor Test and Verification, MTV 2012, Austin, TX, USA, December 10-13, 2012, pp. 76-81, 2012, IEEE Computer Society, 978-1-4673-4441-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | David J. Greaves, Muhammad Mehboob Yasin |
TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL (Selected Papers) ![In: Models, Methods, and Tools for Complex Chip Design - Selected Contributions from FDL 2012, pp. 53-68, 2012, Springer, 978-3-319-01417-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
39 | David J. Greaves, Muhammad Mehboob Yasin |
TLM POWER3: Power estimation methodology for SystemC TLM 2.0. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FDL ![In: Proceeding of the 2012 Forum on Specification and Design Languages, Vienna, Austria, September 18-20, 2012, pp. 106-111, 2012, IEEE, 978-1-4673-1240-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP BibTeX RDF |
|
39 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010, pp. 61-66, 2010, IEEE. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
39 | Dzianis Lukashevich |
Model Order Reduction (MOR) in Transmission Line Matrix (TLM) Method (Anwendung der Modell-Ordnungsreduktion (MOR) auf die Transmission Line Matrix (TLM)-Methode) (PDF / PS) ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2007 |
RDF |
|
37 | Vicente Galiano Ibarra, Marcos Martínez, Héctor Migallón Gomis, David Pérez-Caparrós, Carlos Quesada |
A Case Study in Distributing a SystemC Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN (2) ![In: Distributed Computing, Artificial Intelligence, Bioinformatics, Soft Computing, and Ambient Assisted Living, 10th International Work-Conference on Artificial Neural Networks, IWANN 2009 Workshops, Salamanca, Spain, June 10-12, 2009. Proceedings, Part II, pp. 99-106, 2009, Springer, 978-3-642-02480-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Distributed Systems, MPI, SystemC, PLC, Serialization, TLM, PDES |
37 | Grant Martin |
The First Transaction, but not the Last. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 23(3), pp. 248-249, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SystemC, transaction-level modeling, ESL, TLM |
33 | Huseyin Dogan, Michael Henshaw, Esmond Neil Urwin |
A 'Soft' Approach to TLM Requirements Capture to Support Through-Life Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KSEM ![In: Knowledge Science, Engineering and Management, Third International Conference, KSEM 2009, Vienna, Austria, November 25-27, 2009. Proceedings, pp. 458-469, 2009, Springer, 978-3-642-10487-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Through-Life Management, Soft Systems, Knowledge Management, Requirements Analysis, Interactive Management |
33 | Christian Schröder, Wolfgang Klingauf, Robert Günzel, Mark Burton, Eric Roesler |
Configuration and control of SystemC models using TLM middleware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 81-88, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
OSCI CCI, greenconfig, greencontrol, control, analysis, configuration, inspection, systemc |
33 | Sudipta Kundu, Malay K. Ganai, Rajesh Gupta 0001 |
Partial order reduction for scalable testing of systemC TLM designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 936-941, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation, verification, testing, partial-order reduction |
33 | Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi |
Functional Test-Case Generation by a Control Transaction Graph for TLM Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 157-164, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Wolfgang Ecker, Volkan Esen, Michael Hull |
Execution semantics and formalisms for multi-abstraction TLM assertions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 93-102, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Wolfgang Klingauf, Hagen Gädke, Robert Günzel |
TRAIN: a virtual transaction layer architecture for TLM-based HW/SW codesign of synthesizable MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 1318-1323, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Nicola Bombieri, Franco Fummi, Davide Quaglia |
TLM/network design space exploration for networked embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 58-63, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transaction-level modeling, networked embedded systems |
27 | Yacine Amara, Xavier Marsault |
A GPU Tile-Load-Map architecture for terrain rendering: theory and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Vis. Comput. ![In: Vis. Comput. 25(8), pp. 805-824, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
GPU architecture, Data amplification, Seed model, Level of detail, Terrain rendering |
27 | Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski |
Hardware-dependent software synthesis for many-core embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 304-310, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Luciano Ost, Guilherme Montez Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp da Rosa, Fernando Moraes 0001 |
A high abstraction, high accuracy power estimation model for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
high abstraction modeling, networks-on-chip, power modeling |
27 | David W. Bauer, Christopher D. Carothers, Akintayo Holder |
Scalable Time Warp on Blue Gene Supercomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADS ![In: 23rd International Workshop on Principles of Advanced and Distributed Simulation, PADS 2009, Lake Placid, New York, USA, June 22-25, 2009, pp. 35-44, 2009, IEEE Computer Society, 978-0-7695-3713-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Blue Gene Supercomputer, Time Warp |
27 | Yung-Yuan Chen, Chung-Hsien Hsu, Kuen-Long Leu |
SoC-level risk assessment using FMEA approach in system design with SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIES ![In: IEEE Fourth International Symposium on Industrial Embedded Systems, SIES 2009, Ecole Polytechnique Federale de Lausanne, Switzerland, July 8-10, 2009, pp. 82-89, 2009, IEEE, 978-1-4244-4110-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Sandro Penolazzi, Ahmed Hemani, Luca Bolognino |
A General Approach to High-Level Energy and Performance Estimation in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 200-205, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Giovanni Agosta, Francesco Bruschi, Donatella Sciuto |
Static Analysis of Transaction-Level Communication Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8), pp. 1412-1424, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Yonghyun Hwang, Samar Abdi, Daniel Gajski |
Cycle-approximate Retargetable Performance Estimation at the Transaction Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 3-8, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Alessandro Mignogna, Massimo Conti, M. D'Angelo, Massimo Baleani, Alberto Ferrari |
Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 839-843, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Girish Venkataramani, Seth Copen Goldstein |
Slack analysis in the system design loop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 231-236, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
slack analysis, system design loop, timing update |
27 | Daniel D. Gajski, Samar Abdi, Ines Viskic |
Model Based Synthesis of Embedded Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEUS ![In: Software Technologies for Embedded and Ubiquitous Systems, 6th IFIP WG 10.2 International Workshop, SEUS 2008, Anacarpi, Capri Island, Italy, October 1-3, 2008, Proceedings, pp. 21-33, 2008, Springer, 978-3-540-87784-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Giovanni Beltrame, Donatella Sciuto, Cristina Silvano |
Multi-Accuracy Power and Performance Transaction-Level Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1830-1842, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Ines Viskic, Samar Abdi, Daniel D. Gajski |
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 143-145, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication |
27 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull |
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 767-772, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Grégory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier |
Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 966-971, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Bruno C. Albertini, Sandro Rigo, Guido Araujo, Cristiano C. de Araújo, Edna Barros, Willians Azevedo |
A computational reflection mechanism to support platform debugging in SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007, pp. 81-86, 2007, ACM, 978-1-59593-824-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
debugging, system architecture, platform-based design, computational reflection |
27 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
A methodology for abstracting RTL designs into TL descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 27-29 July 2006, Embassy Suites, Napa, California, USA, pp. 103-112, 2006, IEEE Computer Society, 1-4244-0421-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae |
A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece, pp. 63-68, 2006, IEEE Computer Society, 0-7695-2580-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Nicola Bombieri, Andrea Fedeli, Franco Fummi |
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 127-132, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Wolfgang Klingauf |
Systematic Transaction Level Modeling of Embedded Systems with SystemC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 566-567, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Young-Taek Kim, Taehun Kim, Youngduk Kim, Chulho Shin, Eui-Young Chung, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo |
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 138-139, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Jin Lee, Sin-Chong Park |
Transaction level modeling of IEEE 802.11 system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3978-3981, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Yu-Min Lee, Charlie Chung-Ping Chen |
The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1545-1550, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Rohit Jindal, Kshitiz Jain |
Verification of Transaction-Level SystemC models using RTL Testbenches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMOCODE ![In: 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 24-26 June 2003, Mont Saint-Michel, France, Proceedings, pp. 199-203, 2003, IEEE Computer Society, 0-7695-1923-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Heinz-Josef Schlebusch, Gary Smith 0001, Donatella Sciuto, Daniel Gajski, Carsten Mielenz, Christopher K. Lennard, Frank Ghenassia, Stuart Swan, Joachim Kunkel |
Transaction Based Design: Another Buzzword or the Solution to a Design Problem? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10876-10879, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Haobo Yu, Andreas Gerstlauer, Daniel Gajski |
RTOS scheduling in transaction level models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 31-36, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SpecC, model, system design, RTOS |
23 | P. Ezudheen, Priya Chandran, Joy Chandra, Biju Puthur Simon, Deepak Ravi |
Parallelizing SystemC Kernel for Fast Hardware Simulation on SMP Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PADS ![In: 23rd International Workshop on Principles of Advanced and Distributed Simulation, PADS 2009, Lake Placid, New York, USA, June 22-25, 2009, pp. 80-87, 2009, IEEE Computer Society, 978-0-7695-3713-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
OSCI, Core affinity, SoC, SystemC, SMP, TLM |
23 | Giovanni Beltrame, Cristiana Bolchini, Antonio Miele |
Multi-level fault modeling for transaction-level specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 87-92, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fault modeling, soft error, system-level design, tlm |
23 | Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado |
An open-source binary utility generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 27:1-27:17, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Platform debugging, retargetable tools, TLM |
23 | Thomas Lenart, Henrik Svensson, Viktor Öwall |
A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 398-404, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
SCENIC, Network-on-Chip, Reconfigurable Computing, TLM, 2D Mesh |
23 | Armando Sánchez-Peña, Pedro P. Carballo, Luz García 0001, Antonio Núñez |
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 305-312, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
AMBA 3 AXI, VIPACES, Virtual Components, Verification, Test, System-on-Chip (SoC), IP, DCT, Emulation, SystemC, Environment, TLM, IDCT, VIP |
23 | Alistair C. Bruce, M. M. Kamal Hashmi, Andrew Nightingale, Steve Beavis, Nizar Romdhane, Christopher K. Lennard |
Maintaining consistency between systemC and RTL system designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 85-89, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SPIRIT, transactor, verification, systemC, RTL, TLM, testbench, VIP |
23 | Stuart Swan |
SystemC transaction level models and RTL verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 90-92, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RTL verification, hardware/software co-verification, systemC, hardware/software co-design, transaction level model, TLM |
23 | Wolfgang Klingauf, Robert Günzel, Oliver Bringmann 0001, Pavel Parfuntseu, Mark Burton |
GreenBus: a generic interconnect fabric for transaction level modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 905-910, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
SoC, SystemC, TLM, on-chip communication |
23 | Jae-Gon Lee, Woo-Seung Yang, Young-Su Kwon, Young-Il Kim, Chong-Min Kyung |
Simulation acceleration of transaction-level models for SoC with RTL sub-blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 499-502, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SoC, systemc, transaction-level modeling, TLM, simulation acceleration |
22 | Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl |
System prototypes: virtual, hardware or hybrid? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 1-3, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SystemC TLM, hardware/software co-verification, rapid prototype, embedded software, virtual prototype, virtual platform, system validation, FPGA prototype, system prototype |
22 | D. V. Das |
EM simulation [ICs and MCMs]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 264-267, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
electromagnetic field theory, transmission line matrix methods, integrated circuit packaging, EM simulation, emitted radiation, transmission line matrix method, electromagnetic simulation, TLM method, signal integrity, multichip modules, IC, MCM, electromagnetic field |
20 | Alfonso Salinas, Jorge Porti, Enrique A. Navarro, Sergio Toledo-Redondo, Inmaculada Albert, Aida Castilla, Víctor Montagud-Camps |
A 3D TLM code for the study of the ELF electromagnetic wave propagation in the Earth's atmosphere. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Geosci. ![In: Comput. Geosci. 183, pp. 105499, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Yangjun Wu, Kebin Fang, Dongxiang Zhang, Han Wang, Hao Zhang, Gang Chen 0001 |
TLM: Token-Level Masking for Transformers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2310.18738, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Lukas Jünger 0001, Jan Henrik Weinstock, Rainer Leupers |
Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2023, Hamburg, Germany, September 17-22, 2023, pp. 42-43, 2023, IEEE, 979-8-4007-0289-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
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