Search results for "Trimaran"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
111	Lakshmi N. Chakrapani, John C. Gyllenhaal, Wen-mei W. Hwu, Scott A. Mahlke, Krishna V. Palem, Rodric M. Rabbah	Trimaran: An Infrastructure for Research in Instruction-Level Parallelism.	LCPC	2004	DBLP DOI BibTeX RDF
90	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
38	Meng Wang 0005, Zili Shao, Hui Liu 0006, Chun Jason Xue	Minimizing Leakage Energy with Modulo Scheduling for VLIW DSP Processors.	DIPES	2008	DBLP DOI BibTeX RDF
38	Khaing Khaing Kyi Win, Weng-Fai Wong	Cooperative Instruction Scheduling with Linear Scan Register Allocation.	HiPC	2005	DBLP DOI BibTeX RDF
35	Yuxin Deng, Jinxing Li, Wangqiang Jiang, Min Zhang 0014	Investigation on the Radar Scattering and Doppler Spectrum From Trimaran Based on the Motion of Six Degrees of Freedom.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2023	DBLP DOI BibTeX RDF
35	Bowen Zeng 0001, Yang Song, Linhe Zheng	A Method of a Trimaran Vertical Movements Reduction Control and Hardware Realization.	IEEE Access	2019	DBLP DOI BibTeX RDF
35	Zhilin Liu, Linhe Zheng, Guosheng Li, Bowen Zeng 0001	Vertical Stabilization Control for Trimaran Based on Resultant Force and Moment Distribution.	IEEE Access	2019	DBLP DOI BibTeX RDF
35	Shahid Mahmood, Huang De-bo	Hull Form Optimization of Trimaran Using Genetic Algorithm.	CSE	2011	DBLP DOI BibTeX RDF
35	Yan Peng, Jianda Han	Tracking Control of Unmanned Trimaran Surface Vehicle: Using Adaptive Unscented Kalman Filter to Estimate the Uncertain Parameters.	RAM	2008	DBLP DOI BibTeX RDF
35	Yan Peng, Bo Zhou, Jianda Han	Hardware design and UKF-based tracking control design of Unmanned Trimaran Surface Vehicle.	ROBIO	2007	DBLP DOI BibTeX RDF
19	Weifeng Xu, Russell Tessier	Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors.	ACM Trans. Archit. Code Optim.	2009	DBLP DOI BibTeX RDF	Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
19	Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE (2)	2009	DBLP DOI BibTeX RDF
19	Shu Xiao 0001, Edmund Ming-Kit Lai	A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
19	Yanqin Yang, Zili Shao, Linfeng Pan, Minyi Guo	ISOS: Space Overlapping Based on Iteration Access Patterns for Dynamic Scratch-pad Memory Management in Embedded Systems.	ICYCS	2008	DBLP DOI BibTeX RDF
19	Linfeng Pan, Minyi Guo, Yanqin Yang, Meng Wang 0005, Zili Shao	A State-Based Predictive Approach for Leakage Reduction of Functional Units.	EUC (1)	2008	DBLP DOI BibTeX RDF
19	Shu Xiao 0001, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
19	Weifeng Xu, Russell Tessier	Tetris: a new register pressure control technique for VLIW processors.	LCTES	2007	DBLP DOI BibTeX RDF	register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
19	Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung	SCRF - A Hybrid Register File Architecture.	PaCT	2007	DBLP DOI BibTeX RDF	cluster processor architecture, register architecture, register allocation algorithm, VLIW processor
19	Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Compiler-directed thermal management for VLIW functional units.	LCTES	2006	DBLP DOI BibTeX RDF	VLIW, thermal, IPC
19	Rahul Nagpal, Y. N. Srikant	Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors.	HiPC	2006	DBLP DOI BibTeX RDF
19	Rahul Nagpal, Y. N. Srikant	Compiler-assisted leakage energy optimization for clustered VLIW architectures.	EMSOFT	2006	DBLP DOI BibTeX RDF	scheduling, leakage energy, energy-aware scheduling, clustered VLIW processors
19	Charles Hardnett, Krishna V. Palem, Yogesh Chobe	Compiler optimization of embedded applications for an adaptive SoC architecture.	CASES	2006	DBLP DOI BibTeX RDF	compilers, resource allocation, system on chip, reconfigurable computing, resource scheduling
19	Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo	2D-VLIW: An Architecture Based on the Geometry of Computation.	ASAP	2006	DBLP DOI BibTeX RDF
19	Antoni Portero, Guillermo Talavera, Marius Monton, Borja Martínez, Francky Catthoor, Jordi Carrabina	Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation.	ASAP	2006	DBLP DOI BibTeX RDF
19	Jennifer L. Wong, Weiping Liao, Fei Li 0003, Lei He 0001, Miodrag Potkonjak	Scheduling of Soft Real-Time Systems for Context-Aware Applications.	DATE	2005	DBLP DOI BibTeX RDF
19	Kubilay Atasu, Günhan Dündar, Can C. Özturan	An integer linear programming approach for identifying instruction-set extensions.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	integer linear, programming, ASIPs, extensible processors
19	Jennifer L. Wong, Farinaz Koushanfar, Miodrag Potkonjak	Flexible ASIC: shared masking for multiple media processors.	DAC	2005	DBLP DOI BibTeX RDF	optimization, interconnect, ASIC
19	W. W. S. Chu, Robert G. Dimond, S. Perrott, S. P. Seng, Wayne Luk	Customisable EPIC Processor: Architecture and Tools.	DATE	2004	DBLP DOI BibTeX RDF
19	Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne	Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.	SCOPES	2004	DBLP DOI BibTeX RDF
19	Esther Salamí, Jesús Corbal, Carlos Álvarez 0001, Mateo Valero	Cost effective memory disambiguation for multimedia codes.	CASES	2002	DBLP DOI BibTeX RDF	multimedia, VLIW, run-time analysis, time-to-market, memory disambiguation
19	Tarun Nakra, Rajiv Gupta 0001, Mary Lou Soffa	Value Prediction in VLIW Machines.	ISCA	1999	DBLP DOI BibTeX RDF