Search results for "Turbo-Decoder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
144	André Fonseca dos Santos, Wolfgang Rave, Gerhard P. Fettweis	A Low-Complexity Scheduling for Turbo Equalization with Turbo Decoding.	VTC Spring	2007	DBLP DOI BibTeX RDF
107	Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu	Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
93	Imran Ahmed 0001, Tughrul Arslan	VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond.	ASP-DAC	2007	DBLP DOI BibTeX RDF
80	Jian Liang, Russell Tessier, Dennis Goeckel	A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder.	FCCM	2004	DBLP DOI BibTeX RDF
79	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel	High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Block turbo decoding, Full-parallel architecture, Complexity analysis, FPGA implementation
76	John MacLaren Walsh, Phillip A. Regalia, C. Richard Johnson Jr.	Turbo Decoding as Iterative Constrained Maximum-Likelihood Sequence Detection.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
74	Wai-Chi Fang, Anand Sethuraman, K. Belevi	VLSI design of turbo decoder for integrated communication system-on-chip applications.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
71	Michael J. Thul, Frank Gilbert, Timo Vogt, Gerd Kreiselmaier, Norbert Wehn	A Scalable System Architecture for High-Throughput Turbo-Decoders.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	wireless, VLSI architectures, interleaving, high-throughput, Turbo-Decoder, parallel decoding
68	Ali Al-Shaikhi, Jacek Ilow, Xin Liao	An Adaptive FEC-based Packet Loss Recovery Scheme Using RZ Turbo Codes.	CNSR	2007	DBLP DOI BibTeX RDF
66	Matthias May, Christian Neeb, Norbert Wehn	Evaluation of High Throughput Turbo-Decoder Architectures.	ISCAS	2007	DBLP DOI BibTeX RDF
66	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel	Towards Gb/s turbo decoding of product code onto an FPGA device.	ISCAS	2007	DBLP DOI BibTeX RDF
63	Zhongfeng Wang, Yiyan Tang, Yuke Wang	Low hardware complexity parallel turbo decoder architecture.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
63	Sheetal Kalyani, Vimal Raj, Krishnamurthy Giridhar	Narrowband Interference Mitigation in Turbo-Coded OFDM Systems.	ICC	2007	DBLP DOI BibTeX RDF
63	Yuan Lin 0002, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Alastair Reid 0001, Krisztián Flautner	Design and Implementation of Turbo Decoders for Software Defined Radio.	SiPS	2006	DBLP DOI BibTeX RDF
63	Minyue Fu 0001	Stochastic analysis of turbo decoding.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
61	Yang Sun 0001, Yuming Zhu, Manish Goel, Joseph R. Cavallaro	Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards.	ASAP	2008	DBLP DOI BibTeX RDF
61	Haisheng Liu, Jean-Philippe Diguet, Christophe Jégo, Michel Jézéquel, Emmanuel Boutillon	Energy Efficient Turbo Decoder with Reduced State Metric Quantization.	SiPS	2007	DBLP DOI BibTeX RDF
61	Ji-Hoon Kim, In-Cheol Park	Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
60	Osamu Muta, Yoshihiko Akaiwa	A Weighting Factor Estimation Scheme for Phase-Control based Peak Power Reduction of Turbo-coded OFDM signal.	VTC Spring	2006	DBLP DOI BibTeX RDF
58	Indrajit Atluri, Tughrul Arslan	Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation.	ISVLSI	2004	DBLP DOI BibTeX RDF
57	Kalle Ruttik	Combining BICM with trellis based constellation shaping.	IWCMC	2009	DBLP DOI BibTeX RDF	constellation shaping, turbo decoding, high data rate
55	Erwan Piriou, Christophe Jégo, Patrick Adde, Raphaël Le Bidan, Michel Jézéquel	Efficient architecture for Reed Solomon block turbo code.	ISCAS	2006	DBLP DOI BibTeX RDF
54	Yi-Nan Lin, Wei-Wen Hung, Wei-Chen Lin, Tsan-Jieh Chen, Erl-Huei Lu	An Efficient Soft-Input Scaling Scheme for Turbo Decoding.	SUTC (2)	2006	DBLP DOI BibTeX RDF	adaptive scaling scheme, sign difference ratio (SDR) technique, coding gain improvement, Turbo decoder
54	Michael J. Thul, Norbert Wehn	FPGA implementation of parallel turbo-decoders.	SBCCI	2004	DBLP DOI BibTeX RDF	wireless, parallel architecture, FPGA implementation, turbo-decoder
54	Yiqing Zhou 0001, Jiangzhou Wang	Downlink transmission of broadband OFCDM systems-part IV: soft decision.	IEEE J. Sel. Areas Commun.	2006	DBLP DOI BibTeX RDF
52	Ji-Hoon Kim, In-Cheol Park	Duo-binary circular turbo decoder based on border metric encoding for WiMAX.	ASP-DAC	2008	DBLP DOI BibTeX RDF
52	Myoung-Cheol Shin, In-Cheol Park	SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
52	Jian Gu, Yi Zhang, Dacheng Yang, Zhen Liu	Adaptive Iterative Turbo Decoding Algorithm.	VTC Spring	2006	DBLP DOI BibTeX RDF
50	Wen-Ta Lee, San-Ho Lin, Chia-Chun Tsai, Trong-Yen Lee, Yuh-Shyan Hwang	A new low-power turbo decoder using HDA-DHDD stopping iteration.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
50	Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel	Design of a High-Speed Asynchronous Turbo Decoder.	ASYNC	2007	DBLP DOI BibTeX RDF
49	Yossef Rahamim, Avraham Freedman, Arie Reichman	ML iterative soft-decision-directed (ML-ISDD): a carrier synchronization system for short packet turbo coded communication.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
49	Xizhong Lou, Yanmin Chen	Pipelined Parallel Architectures for High Throughput Turbo Decoding.	APCCAS	2006	DBLP DOI BibTeX RDF
47	Sook Min Park, Jaeyoung Kwak, Kwyro Lee	Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation.	VTC Spring	2008	DBLP DOI BibTeX RDF
47	Libero Dinoi, Sergio Benedetto	Variable-size interleaver design for parallel turbo decoder architectures.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
47	Imran Ahmed 0001, Tughrul Arslan, Sajid Baloch, Ian Underwood, Robin Woodburn	Domain Specific Reconfigurable Architecture of Turbo Decoder Optimized for Short Distance Wireless Communication.	IPDPS	2005	DBLP DOI BibTeX RDF
47	Jaeyoung Kwak, Sook Min Park, Sang-Sic Yoon, Kwyro Lee	Implementation of a parallel turbo decoder with dividable interleaver.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
46	Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer	Area-efficient high-throughput MAP decoder architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
46	Lina Fagoonee, Bahram Honary	A Multifunctional Turbo-Based Receiver Using Partial Unit Memory Codes.	IMACC	2003	DBLP DOI BibTeX RDF
44	Zhiyong He, Sébastien Roy 0002, Paul Fortier	High-speed and low-power design of parallel turbo decoder.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
44	Imran Ahmed 0001, Tughrul Arslan	A Reconfigurable Viterbi Decoder for a Communication Platform.	FPL	2006	DBLP DOI BibTeX RDF
43	Guang-Chong Zhu, Fady Alajaji	Joint source-channel turbo coding for binary Markov sources.	IEEE Trans. Wirel. Commun.	2006	DBLP DOI BibTeX RDF
43	Erwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel	A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes.	ISVLSI	2006	DBLP DOI BibTeX RDF
43	Li X. Zhang, Alister G. Burr	Iterative carrier phase recovery suited to turbo-coded systems.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
43	Ibrahim Al-Mohandes, M. L. Elmasry	Iteration reduction of turbo decoders using an efficient stopping/cancellation technique.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
41	Tsung-Han Tsai 0001, Cheng-Hung Lin, An-Yeu Wu	A memory-reduced log-MAP kernel for turbo decoder.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
41	Andrea Xotta, Daniele Vogrig, Andrea Gerosa, Andrea Neviani, Alexandre Graell i Amat, Guido Montorsi, Melchiorre Bruccoleri, Giorgio Betti	An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
41	Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni	A 50 Mbit/s Iterative Turbo-Decoder.	DATE	2000	DBLP DOI BibTeX RDF
38	Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa	Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
38	Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa	Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
38	Jong Hun Han, Ahmet T. Erdogan, Tughrul Arslan	High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization.	ISVLSI	2005	DBLP DOI BibTeX RDF
38	Matthieu Arzel, Cyril Lahuec, Fabrice Seguin, David Gnaedig, Michel Jézéquel	. Analog slice turbo decoding.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
38	Qihui Wu, Chunming Zhao, Jinlong Wang	Turbo iterative equalization for HSDPA systems.	Sci. China Ser. F Inf. Sci.	2007	DBLP DOI BibTeX RDF	chip equalization, multi-code detection, turbo processing, HSDPA, turbo code
38	Lei Li, Qin Wang, Cheng Youn Lu	A Novel Stopping Criterion for Turbo Decoding.	ICICIC (1)	2006	DBLP DOI BibTeX RDF
38	Seokhyun Yoon, Yeheskel Bar-Ness	Packet data communications over coded CDMA. Part I: achievable spectral efficiency of CDMA systems with turbo codes and linear multiuser receivers.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
38	Frank Gilbert, Norbert Wehn	Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders.	PATMOS	2003	DBLP DOI BibTeX RDF
35	Jungpil Yu, Marie-Laure Boucheret, Robert Vallet, Alban Duverdier, Gilles Mesnager	Interleaver design for turbo codes from convergence analysis.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
35	Catherine Dezan, Christophe Jégo, Bernard Pottier, Christophe Gouyen, Loïc Lagadec	The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA.	HICSS	2006	DBLP DOI BibTeX RDF
35	Dong-Soo Lee, In-Cheol Park	Low-power log-MAP turbo decoding based on reduced metric memory access.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
33	Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
33	Alberto La Rosa, Luciano Lavagno, Claudio Passerone	Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
33	Fengfan Yang, Tho Le-Ngoc	GGD model of extrinsic information with dynamic parameter assignment for turbo decoder.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
33	Alberto La Rosa, Claudio Passerone, Francesco Gregoretti, Luciano Lavagno	Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform.	DATE	2004	DBLP DOI BibTeX RDF
33	Zhipei Chi, Leilei Song, Keshab K. Parhi	A study on the performance, complexity tradeoffs of block turbo decoder design.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
33	Jonathan Roth, Naraig Manjikian, Subramania Sudharsanan	Performance optimization and parallelization of turbo decoding for software-defined radio.	CCECE	2009	DBLP DOI BibTeX RDF
33	Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta	A highly parallel Turbo Product Code decoder without interleaving resource.	SiPS	2008	DBLP DOI BibTeX RDF
33	Jah-Ming Hsu, Chin-Liang Wang	On finite-precision implementation of a decoder for turbo codes.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
30	Hedaia Ghannam, Izzat Darwazeh	Comparison of turbo decoder and turbo equalizer for spectrally efficient FDM system.	CSNDSP	2016	DBLP DOI BibTeX RDF
30	Maurizio Martina, Guido Masera	Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
30	Maurizio Martina, Guido Masera	Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures	CoRR	2009	DBLP BibTeX RDF
30	Alexandre Graell i Amat, Sergio Benedetto, Guido Montorsi, Daniele Vogrig, Andrea Neviani, Andrea Gerosa	An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code.	ICC	2005	DBLP DOI BibTeX RDF
30	Kalle Ruttik	BER for CMOS Analog Decoder with Different Working Points.	ICT	2004	DBLP DOI BibTeX RDF
30	Yeong-Luh Ueng, Yenming J. Chen	A Turbo Coded MIMO Scheme for Noncoherent Fast-Fading Channels.	VTC Spring	2008	DBLP DOI BibTeX RDF
30	Kyeong Jin Kim, Ronald A. Iltis	Iterative Soft-Kalman Filter-based Data Detection and Channel Estimation for Turbo Coded MIMO-OFDM Systems.	Int. J. Wirel. Inf. Networks	2007	DBLP DOI BibTeX RDF	Kalman filtering, OFDM, MIMO, Turbo Codes
30	Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park	Low-power hybrid turbo decoding based on reverse calculation.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Pablo Ituero, Marisa López-Vallejo	New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.	ASAP	2006	DBLP DOI BibTeX RDF
30	Zhipei Chi, Zhongfeng Wang, Keshab K. Parhi	On the better protection of short-frame turbo codes.	IEEE Trans. Commun.	2004	DBLP DOI BibTeX RDF
30	Akinori Nakajima, Deepshikha Garg, Fumiyuki Adachi	Turbo coded MIMO multiplexing with iterative adaptive soft parallel interference cancellation.	VTC Fall (2)	2004	DBLP DOI BibTeX RDF
29	Matthew F. Brejza, Wenbo Zhang, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo	Adaptive iterative detection for expediting the convergence of a serially concatenated Unary Error Correction decoder, turbo decoder and an iterative demodulator.	ICC	2015	DBLP DOI BibTeX RDF
29	Ya-Cheng Lu, Erl-Huei Lu	Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder.	IEICE Trans. Commun.	2010	DBLP DOI BibTeX RDF
27	Joong-gon Ryu, Jun Heo, Pansoo Kim, Ho-Jin Lee	Iterative Phase Offst Estimation for Mobile Broadband Satellite Internet Systems.	VTC Spring	2006	DBLP DOI BibTeX RDF
27	Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni	VLSI architectures for turbo codes.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
25	Mayank Tiwari 0002, Yuming Zhu, Chaitali Chakrabarti	Memory sub-banking scheme for high throughput MAP-based SISO decoders.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
25	Marion Jeanne, Jean-Claude Carlach, Pierre Siohan	Joint source-channel decoding of variable-length codes for convolutional codes and turbo codes.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
25	Yannick Saouter, Claude Berrou	Fast soft-output Viterbi decoding for duo-binary turbo codes.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
22	Helge Lüders, Andreas Minwegen, Peter Vary	Improving UMTS LTE Performance by UEP in High Order Modulation.	MCSS	2009	DBLP DOI BibTeX RDF
22	Katsunari Honjo, Tomoaki Ohtsuki	LLR Based Iterative Reduced-Complexity MLD Algorithm with Parallel Interference Cancellation (PIC) in MIMO Systems.	VTC Spring	2007	DBLP DOI BibTeX RDF
22	Zhuo Xue, Kok-Keong Loo, John Cosmas	Embedded Side Information Refinement for Pixel Domain Wyner-Ziv Video Coding Towards UMTS 3G Application.	ICME	2007	DBLP DOI BibTeX RDF
22	M. Nabipoor, S. A. Khodaian, Naser Sedaghati-Mokhtari, Sied Mehdi Fakhraie, Seyed Hamaidreza Jamali	A High-Speed Low-Complexity VLSI SISO Architecture.	APCCAS	2006	DBLP DOI BibTeX RDF
22	Carl Fredrik Leanderson, Carl-Erik W. Sundberg	The max-log list algorithm (MLLA)-a list-sequence decoding algorithm that provides soft-symbol output.	IEEE Trans. Commun.	2005	DBLP DOI BibTeX RDF
22	Xinyu Gu, Kai Niu 0001, Weiling Wu	A Novel Efficient Soft Output Demodulation Algorithm for High Order Modulation.	CIT	2004	DBLP DOI BibTeX RDF
22	Frank Gilbert, Michael J. Thul, Norbert Wehn	Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors .	DATE	2003	DBLP DOI BibTeX RDF
22	Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch	Hardware/Software Trade-Offs for Advanced 3G Channel Coding.	DATE	2002	DBLP DOI BibTeX RDF
20	Amitava Middya, Terng-Yin Hsu	Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding.	Integr.	2023	DBLP DOI BibTeX RDF
20	Miguel Ángel Pérez Naranjo, Víctor P. Gil Jiménez	CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation.	IEEE Access	2023	DBLP DOI BibTeX RDF
20	Li Zhang, Weihong Fu, Fan Shi, Chunhua Zhou, Yongyuan Liu	A Parallel Turbo Decoder Based on Recurrent Neural Network.	Wirel. Pers. Commun.	2022	DBLP DOI BibTeX RDF
20	Ganesh Yellapu	Moderate Complexity Turbo Decoder for Near-Optimum Decoding of Product Codes.	VTC Spring	2022	DBLP DOI BibTeX RDF
20	Ming Zhan, Zhibo Pang, Kan Yu, Hong Wen 0001	Reverse Calculation-Based Low Memory Turbo Decoder for Power Constrained Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
20	Yihan Jiang, Hyeji Kim, Himanshu Asnani, Sreeram Kannan, Sewoong Oh, Pramod Viswanath	DeepTurbo: Deep Turbo Decoder.	CoRR	2019	DBLP BibTeX RDF
20	Jun Li 0065, Xiumin Wang, Jinlong He, Chen Su, Liang Shan 0002	Turbo Decoder Design based on an LUT-Normalized Log-MAP Algorithm.	Entropy	2019	DBLP DOI BibTeX RDF
20	Cheng-Hung Lin, Ching-Wen Hsieh	Low-Routing-Complexity Convolutional/Turbo Decoder Design for Iterative Detection and Decoding Receivers.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF